iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Improvements in assertpmux	Clifford Wolf	2016-09-07	1	-0/+3
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*	Removed $predict again	Clifford Wolf	2016-08-28	1	-1/+0
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*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-0/+2
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*	A few modifications after pull request comments	Ruben Undheim	2016-06-18	1	-2/+1
\| \| \| \| \|	- Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h
*	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	1	-0/+2
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*	Added addBufGate module method	Clifford Wolf	2016-02-02	1	-0/+2
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*	Meaningless coding style change	Clifford Wolf	2016-01-31	1	-1/+0
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*	rtlil: duplicate remove2() for std::set<>	Rick Altherr	2016-01-29	1	-0/+2
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*	rtlil: change IdString comparison operators to take references instead of copies	Rick Altherr	2016-01-29	1	-3/+3
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*	Removed dangling ';' in rtlil.h	Clifford Wolf	2015-11-26	1	-2/+2
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*	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	Clifford Wolf	2015-10-24	1	-1/+2
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*	Cosmetic fix in Module::addLut()	Clifford Wolf	2015-09-18	1	-1/+1
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*	Added $tribuf and $_TBUF_ cell types	Clifford Wolf	2015-08-16	1	-0/+1
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*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-1/+1
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-11/+11
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*	Added design->rename(module, new_name)	Clifford Wolf	2015-06-30	1	-0/+1
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*	Added "rename -top new_name"	Clifford Wolf	2015-06-17	1	-0/+1
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*	Added $eq/$neq -> $logic_not/$reduce_bool optimization	Clifford Wolf	2015-04-29	1	-0/+1
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*	Improved attributes API and handling of "src" attributes	Clifford Wolf	2015-04-24	1	-23/+18
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*	Added support for initialized brams	Clifford Wolf	2015-04-06	1	-1/+10
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*	Added "dffinit", Support for initialized Xilinx DFF	Clifford Wolf	2015-04-04	1	-0/+1
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*	Some cleanups in "clean"	Clifford Wolf	2015-02-24	1	-0/+8
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*	Added SigSpec::has_const()	Clifford Wolf	2015-02-08	1	-0/+1
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*	Added cell->known(), cell->input(portname), cell->output(portname)	Clifford Wolf	2015-02-07	1	-0/+5
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*	Added "equiv_make -blacklist <file> -encfile <file>"	Clifford Wolf	2015-01-31	1	-0/+1
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*	Synced RTLIL::unescape_id() to log_id() behavior	Clifford Wolf	2015-01-30	1	-3/+9
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*	Added dict/pool.sort()	Clifford Wolf	2015-01-24	1	-0/+4
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*	Added equiv_make command	Clifford Wolf	2015-01-19	1	-1/+2
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*	Removed SigSpec::extend_xx() api	Clifford Wolf	2015-01-01	1	-1/+0
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*	Progress in memory_bram	Clifford Wolf	2014-12-31	1	-5/+5
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*	IdString optimization	Clifford Wolf	2014-12-31	1	-0/+6
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*	added hashlib::mkhash_init	Clifford Wolf	2014-12-30	1	-1/+1
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*	Added "yosys -X"	Clifford Wolf	2014-12-29	1	-0/+11
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*	Converting "share" to dict<> and pool<> complete	Clifford Wolf	2014-12-29	1	-2/+9
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*	Added mkhash_xorshift()	Clifford Wolf	2014-12-29	1	-2/+3
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*	Fixed performance bug in object hashing	Clifford Wolf	2014-12-28	1	-1/+1
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*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28	1	-5/+26
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*	More dict/pool related changes	Clifford Wolf	2014-12-27	1	-2/+2
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*	More hashtable finetuning	Clifford Wolf	2014-12-27	1	-3/+5
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*	Replaced std::unordered_set (nodict) with Yosys::pool	Clifford Wolf	2014-12-26	1	-113/+19
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*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26	1	-2/+30
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*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-263/+357
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*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-1/+1
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*	Added support for multiple clock domains to "abc" pass	Clifford Wolf	2014-12-21	1	-0/+1
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*	Fixed build with gcc 4.6	Clifford Wolf	2014-12-16	1	-1/+1
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*	Added IdString::destruct_guard hack	Clifford Wolf	2014-12-11	1	-0/+13
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*	Added bool constructors to SigBit and SigSpec	Clifford Wolf	2014-12-08	1	-0/+2
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*	Added module->addDffe() and module->addDffeGate()	Clifford Wolf	2014-12-08	1	-0/+2
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*	Improved TopoSort determinism	Clifford Wolf	2014-11-07	1	-1/+1
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*	Fixed a few VS warnings	Clifford Wolf	2014-10-17	1	-1/+1
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