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* Be more conservative with new const-function codeClifford Wolf2014-02-141-1/+5
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* Added support for FOR loops in function calls in parametersClifford Wolf2014-02-143-0/+43
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* Created basic support for function calls in parameter valuesClifford Wolf2014-02-144-49/+184
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* Implemented read_verilog -deferClifford Wolf2014-02-133-59/+90
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* Added support for functions returning integerClifford Wolf2014-02-121-2/+12
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* renamed ilang "scope error" to "ilang error"Clifford Wolf2014-02-111-9/+9
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* Improved ilang parser error messagesClifford Wolf2014-02-091-9/+9
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* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-061-1/+1
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* Added read_verilog -setattrClifford Wolf2014-02-051-0/+15
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* Fixed bug in sequential sat proofs and improved handling of assertsClifford Wolf2014-02-041-0/+2
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-0/+1
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* Added support for blanks after -I and -D in read_verilogClifford Wolf2014-02-021-7/+20
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* Fixed comment/eol parsing in ilang frontendClifford Wolf2014-02-012-22/+25
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* Added constant size expression support of sized constantsClifford Wolf2014-02-015-0/+44
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* Bugfix in name resolution with generate blocksClifford Wolf2014-01-301-1/+1
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* Added read_verilog -icells optionClifford Wolf2014-01-294-6/+20
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* Fixed handling of unsized constants in verilog frontendClifford Wolf2014-01-241-2/+2
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* Fixed algorithmic complexity of AST simplification of long expressionsClifford Wolf2014-01-203-6/+13
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* Added $assert cellClifford Wolf2014-01-192-0/+92
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* Added Verilog parser support for assertsClifford Wolf2014-01-194-3/+12
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* Fixed parsing of verilog macros at end of lineClifford Wolf2014-01-181-1/+1
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* Added verilog_defaults commandClifford Wolf2014-01-171-0/+66
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* Fixed typo in frontends/ast/simplify.ccClifford Wolf2014-01-121-1/+1
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* Added updating of RTLIL::autoidx to ilang frontendClifford Wolf2014-01-031-1/+23
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* Added correct handling of $memwr priorityClifford Wolf2014-01-031-0/+2
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* Fixed a stupid access after delete bugClifford Wolf2013-12-291-1/+2
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* Fixed parsing of non-arg macro calls followed by "("Clifford Wolf2013-12-271-1/+7
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* Fixed parsing of macros with no arguments and expansion text starting with "("Clifford Wolf2013-12-271-1/+2
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* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-271-2/+2
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* Added proper === and !== support in constant expressionsClifford Wolf2013-12-276-15/+37
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* Added elsif preproc supportClifford Wolf2013-12-181-1/+14
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* Added support for macro argumentsClifford Wolf2013-12-181-23/+75
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* Keep strings as strings in const ternary and concatClifford Wolf2013-12-053-5/+25
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* Added const folding support for $signed and $unsignedClifford Wolf2013-12-051-0/+7
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* Added AstNode::mkconst_str APIClifford Wolf2013-12-053-12/+19
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* Fixed generate-for (and disabled double warning for auto-wire)Clifford Wolf2013-12-041-1/+5
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* Added support for $clog2 system functionClifford Wolf2013-12-041-4/+20
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* Various improvements in support for generate statementsClifford Wolf2013-12-046-7/+134
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-044-8/+4
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-043-24/+37
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* Added support for local regs in named blocksClifford Wolf2013-12-043-2/+30
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* Fixed temp net name generation in rtlil process generator for abbreviated ↵Clifford Wolf2013-11-281-0/+2
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* Added "src" attribute to processesClifford Wolf2013-11-281-0/+1
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* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-241-1/+5
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* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-243-5/+19
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* Early wire/reg/parameter width calculation in ast/simplifyClifford Wolf2013-11-241-0/+5
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* Added support for signed parameters in ilangClifford Wolf2013-11-242-1/+8
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* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-245-56/+4
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* Implemented correct handling of signed module parametersClifford Wolf2013-11-243-3/+7
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* Improved handling of initialized registersClifford Wolf2013-11-231-10/+10
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