aboutsummaryrefslogtreecommitdiffstats
path: root/frontends
Commit message (Collapse)AuthorAgeFilesLines
* ilang_lexer: fix check for out of range literal.whitequark2020-05-291-1/+3
| | | | Commit ca70a104 did not use a correct check.
* Silence spurious warning in Verilog lexer when compiling with GCCRupert Swarbrick2020-05-261-1/+3
| | | | | | | The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL.
* verilog: move attr from simple_behav_stmt to its children to attachEddie Hung2020-05-251-13/+17
|
* verilog: do not warn for attributes on null statementsEddie Hung2020-05-251-2/+0
|
* verilog: handle empty generate statement by removing gen_stmt_or_null...Eddie Hung2020-05-251-7/+8
| | | | | ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay.
* verilog: fix #2037 by permitting (and freeing) attributes on null stmtEddie Hung2020-05-251-1/+5
|
* Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-211-11/+9
|\ | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
| * Update frontends/verilog/verilog_parser.yEddie Hung2020-05-211-1/+1
| | | | | | Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
| * verilog: attributes before task enable (but 13 s/r conflicts)Eddie Hung2020-05-141-10/+8
| |
* | Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-1/+20
| | | | | | | | Fixes #2058.
* | Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dffEddie Hung2020-05-182-4/+12
|\ \ | | | | | | abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
| * | aiger: -xaiger to return $_FF_ flopsEddie Hung2020-05-141-15/+2
| | |
| * | aiger/xaiger: use odd for negedge clk, even for posedgeEddie Hung2020-05-141-4/+3
| | | | | | | | | | | | Since abc9 doesn't like negative mergeability values
| * | aiger: -xaiger to parse initial state back into (* init *) on Q wireEddie Hung2020-05-141-1/+2
| | |
| * | aiger: -xaiger to read $_DFF_[NP]_ back with new clocks createdEddie Hung2020-05-142-3/+24
| | | | | | | | | | | | according to mergeability class, and init state as cell attr
* | | Revert "Add support for non-power-of-two mem chunks in verific importer"Claire Wolf2020-05-171-12/+2
|/ / | | | | | | This reverts commit 173aa27ca5ef6e7c0a9277e8da7765adcd63bfe9.
* | Merge pull request #2045 from YosysHQ/eddie/fix2042Eddie Hung2020-05-141-1/+13
|\ \ | | | | | | verilog: error if no direction given for task arguments, default to input in SV mode
| * | verilog: default to input in sv mode if task/func has no dir ...Eddie Hung2020-05-131-2/+10
| | | | | | | | | | | | otherwise error
| * | verilog: error out when non-ANSI task/func argumentsEddie Hung2020-05-111-1/+5
| |/
* | Merge pull request #2052 from YosysHQ/claire/verific_memfixClaire Wolf2020-05-141-2/+12
|\ \ | | | | | | Add support for non-power-of-two mem chunks in verific importer
| * | Add support for non-power-of-two mem chunks in verific importerClaire Wolf2020-05-141-2/+12
| |/ | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-141-1/+1
|\ \ | |/ |/| ast: swap range regardless of range_left >= 0
| * ast: swap range regardless of range_left >= 0Eddie Hung2020-05-041-1/+1
| |
* | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-082-4/+5
|\ \ | | | | | | Avoid switch fall-through warnings
| * | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-072-4/+5
| | | | | | | | | | | | | | | C++17 introduced [[fallthrough]], GCC and clang had their own vendored attributes before that. MSVC doesn't seem to have such a warning at all.
* | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-075-16/+82
|\ \ \ | |/ / |/| | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * | Fix handling of signed indices in bit slicesClaire Wolf2020-05-021-3/+8
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-025-7/+22
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-024-7/+53
| | | | | | | | | | | | | | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #2028 from zachjs/masterEddie Hung2020-05-061-1/+6
|\ \ \ | | | | | | | | verilog: allow null gen-if then block
| * | | verilog: allow null gen-if then blockZachary Snow2020-05-061-1/+6
| | |/ | |/|
* | | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanupEddie Hung2020-05-056-31/+31
|\ \ \ | | | | | | | | frontend: cleanup to use more ID::*, more dict<> instead of map<>
| * | | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-046-31/+31
| |/ /
* | | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-052-2/+6
|\ \ \ | | | | | | | | verilog: set src attribute for primitives
| * | | verilog: set src attribute for primitivesEddie Hung2020-05-042-2/+6
| |/ /
* / / verilog: fix specify src attributeEddie Hung2020-05-041-18/+20
|/ /
* | Merge pull request #1996 from boqwxp/rtlil_source_locationsEddie Hung2020-05-041-13/+13
|\ \ | | | | | | frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
| * | frontend: Include complete source location instead of just ↵Alberto Gonzalez2020-05-011-13/+13
| | | | | | | | | | | | `location.first_line` in `frontends/ast/genrtlil.cc`.
* | | aiger: fixes for ports that have start_offset != 0Eddie Hung2020-05-021-30/+47
| |/ |/|
* | Merge pull request #2001 from whitequark/wasiwhitequark2020-05-011-1/+1
|\ \ | | | | | | Add WASI platform support
| * | Add WASI platform support.whitequark2020-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This includes the following significant changes: * Patching ezsat and minisat to disable resource limiting code on WASM/WASI, since the POSIX functions they use are unavailable. * Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform does not support spawning subprocesses (i.e. Emscripten or WASI). This definition hides the definition of `run_command()`. * Adding a new Makefile flag, DISABLE_SPAWN, present in the same condition. This flag disables all passes that require spawning subprocesses for their function.
* | | Merge pull request #1981 from YosysHQ/claire/fix1837Claire Wolf2020-05-011-0/+4
|\ \ \ | |/ / |/| | Clear current_scope when done with RTLIL generation
| * | Clear current_scope when done with RTLIL generation, fixes #1837Claire Wolf2020-04-221-0/+4
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | verific: ignore anonymous enumsEddie Hung2020-04-301-1/+4
| | |
* | | verific: support VHDL enums tooEddie Hung2020-04-271-13/+43
| | |
* | | verific: recover wiretype/enum attr as part of import_attributes()Eddie Hung2020-04-272-6/+35
| | |
* | | Revert "verific: import enum attributes from verific"Eddie Hung2020-04-241-24/+0
| |/ |/| | | | | This reverts commit 5028e17f7db11f901ce9e423dfe2c6f7e68259cc.
* | verific: do not assert if wire not found; warn insteadEddie Hung2020-04-231-2/+6
| |
* | verific: import enum attributes from verificEddie Hung2020-04-221-0/+20
|/
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-213-5/+13
| | | | Fixes #1819, #1820.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 12:15:22 +0000