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* Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-214-15/+207
|\ | | | | Improved rewrite code for writing to bit slice
| * Make mask-and-shift the default for bitselwriteClaire Wolf2020-04-161-1/+1
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-164-4/+144
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * Improved rewrite code for writing to bit slice (disabled for now)Claire Wolf2020-04-151-12/+64
| | | | | | | | | | | | | | | | | | This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #1961 from whitequark/paramod-original-namewhitequark2020-04-212-0/+5
|\ \ | | | | | | ast, rpc: record original name of $paramod\* as \hdlname attribute
| * | ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-182-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute.
* | | Extend support for format strings in Verilog front-endClaire Wolf2020-04-181-8/+38
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Set Verilog source location for explicit blocks (`begin` ... `end`).Alberto Gonzalez2020-04-171-0/+1
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* | | Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` ↵Alberto Gonzalez2020-04-171-0/+2
|/ / | | | | | | nodes.
* | Add location information to `AST_CONSTANT` nodes.Alberto Gonzalez2020-04-161-0/+3
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* | ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-162-2/+7
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1918 from whitequark/simplify-improve_enumwhitequark2020-04-151-5/+3
|\ | | | | ast/simplify: improve enum handling
| * ast/simplify: improve enum handling.whitequark2020-04-151-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, enum values were serialized as attributes of form \enum_<width>_<value> where <value> was a decimal signed integer. This has multiple drawbacks: * Enums with large values would be hard to process for downstream tooling that cannot parse arbitrary precision decimals. (In fact Yosys also did not correctly process enums with large values, and would overflow `int`.) * Enum value attributes were not confined to their own namespace, making it harder for downstream tooling to enumerate all such attributes, as opposed to looking up any specific value. * Enum values could not include x or z, which are explicitly permitted in the SystemVerilog standard. After this commit, enum values are serialized as attributes of form \enum_value_<value> where <value> is a bit sequence of the appropriate width.
* | Fix 5bba9c3, closes #1876Claire Wolf2020-04-141-7/+13
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-142-1/+25
|\ \ | | | | | | support using previously declared types/localparams/parameters in package
| * | support using previously declared types/localparams/params in packageJeff Wang2020-04-072-1/+25
| | | | | | | | | | | | | | | | | | | | | (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
* | | Merge pull request #1880 from jjj11x/duplicate_enumwhitequark2020-04-141-2/+3
|\ \ \ | |_|/ |/| | duplicated enum item names should result in an error
| * | duplicated enum item names should result in an errorJeff Wang2020-04-071-2/+3
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* | Merge pull request #1910 from boqwxp/cleanup_ilang_parserwhitequark2020-04-131-4/+4
|\ \ | | | | | | Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
| * | Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.Alberto Gonzalez2020-04-131-4/+4
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* | | verilog: Fix write to deleted objectDavid Shah2020-04-121-1/+0
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1875 from whitequark/read_ilang-int_overflowwhitequark2020-04-092-2/+14
|\ \ | | | | | | Improve handling of integer literals in RTLIL frontend
| * | read_ilang: improve style. NFC.whitequark2020-04-061-2/+1
| | | | | | | | | Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
| * | read_ilang: improve error message for overly long wires.whitequark2020-04-061-0/+3
| | | | | | | | | | | | Fixes #1838.
| * | read_ilang: detect overflow of integer literals.whitequark2020-04-061-1/+11
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* / aigerparse: only define __STDC_FORMAT_MACROS it not already before.Henner Zeller2020-04-071-0/+2
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* Merge pull request #1853 from YosysHQ/eddie/fix_dynsliceEddie Hung2020-04-021-1/+2
|\ | | | | ast: cap dynamic range select to size of signal, suppresses warnings
| * ast: cap dynamic range select to size of signal, suppresses warningsEddie Hung2020-04-011-1/+2
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* | Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-029-449/+437
|\ \ | | | | | | IdString: use more ID::*, make them easier to use, speed up IdString::in()
| * | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-028-313/+301
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| * | kernel: use more ID::*Eddie Hung2020-04-029-142/+142
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* | | Merge pull request #1846 from dh73/ast_feClaire Wolf2020-04-021-0/+3
|\ \ \ | |/ / |/| | Adding error message for when size (width) of number literal is zero
| * | Replacing log_error for log_file_error due consistencyDiego H2020-03-311-2/+1
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| * | Adding error message for when size (width) of number literal is zeroDiego H2020-03-301-0/+4
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* | | Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-023-38/+44
|\ \ \ | | | | | | | | kernel: speedup by using more pass-by-const-ref
| * | | kernel: more pass by const ref, more speedupsEddie Hung2020-03-183-38/+44
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* | | | Merge pull request #1844 from YosysHQ/dave/gen-source-locDavid Shah2020-04-011-0/+6
|\ \ \ \ | | | | | | | | | | verilog: Add location info for generate constructs
| * | | | verilog: Add location info for generate constructsDavid Shah2020-04-011-0/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge pull request #1848 from YosysHQ/eddie/fix_dynsliceClaire Wolf2020-04-011-1/+1
|\ \ \ \ \ | |_|_|/ / |/| | | / | | |_|/ | |/| | ast: simplify to fully populate dynamic slicing case transformation
| * | | ast: simplify to fully populate dynamic slicing case transformationEddie Hung2020-03-311-1/+1
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* | | Merge pull request #1783 from boqwxp/astcc_cleanupEddie Hung2020-03-301-13/+20
|\ \ \ | |_|/ |/| | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
| * | Add explanatory comment about inefficient wire removal and remove ↵Alberto Gonzalez2020-03-301-4/+8
| | | | | | | | | | | | | | | | | | superfluous call to `fixup_ports()`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | Revert over-aggressive change to a more modest cleanup.Alberto Gonzalez2020-03-271-2/+3
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| * | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.Alberto Gonzalez2020-03-191-11/+13
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* | | Merge pull request #1811 from PeterCrozier/typedef_scopeN. Engelhardt2020-03-304-41/+81
|\ \ \ | | | | | | | | Support module/package/interface/block scope for typedef names.
| * | | Inline productions to follow house style.Peter Crozier2020-03-271-33/+29
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| * | | Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-242-3/+11
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| * | | Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-234-20/+56
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* | | | Merge pull request #1778 from rswarbrick/sv-definesN. Engelhardt2020-03-304-149/+578
|\ \ \ \ | | | | | | | | | | Add support for SystemVerilog-style `define to Verilog frontend
| * | | | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-149/+578
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
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