iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add $allconst and $allseq cell types	Clifford Wolf	2018-02-23	3	-4/+6
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Add Verific SVA support for ranges in repetition operator	Clifford Wolf	2018-02-22	1	-5/+26
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*	Add support for SVA throughout via Verific	Clifford Wolf	2018-02-21	1	-2/+6
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*	Add support for SVA sequence concatenation ranges via verific	Clifford Wolf	2018-02-18	1	-16/+124
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Add support for SVA until statements via Verific	Clifford Wolf	2018-02-18	2	-34/+119
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Move Verific SVA importer to extra C++ source file	Clifford Wolf	2018-02-18	4	-1279/+1370
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Merge Verific SVA preprocessor and SVA importer	Clifford Wolf	2018-02-18	1	-79/+44
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2018-02-16	1	-0/+6
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\| *	Improve handling of "bus" pins in liberty front-end (some files use ↵	Clifford Wolf	2018-02-15	1	-0/+6
\| \| \| \| \| \| \| \| \| \| \| \|	bus.pin.direction) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* \|	Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF	Clifford Wolf	2018-02-15	1	-1/+1
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*	Fix single-bit $stable handling in verific front-end	Clifford Wolf	2018-02-01	1	-0/+22
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Add Verific attribute handling for assert/assume/cover/live/fair cells	Clifford Wolf	2018-01-31	1	-10/+16
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Fix permissions on verific vdb files	Clifford Wolf	2018-01-28	1	-0/+1
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*	Fixed handling of synchronous and asynchronous assertion/assumption/cover in ↵	Clifford Wolf	2018-01-23	1	-27/+29
\| \| \| \| \| \|	verific bindings Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Add support for "yosys -E"	Clifford Wolf	2018-01-07	2	-2/+5
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Merge pull request #479 from Fatsie/latch_without_data	Clifford Wolf	2018-01-05	1	-4/+23
\|\ \| \| \| \|	Some standard cell libraries include a latch with only set/reset.
\| *	Some standard cell libraries include a latch with only set/reset.	Staf Verhaegen	2018-01-03	1	-4/+23
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* \|	Bugfix in hierarchy handling of blackbox module ports	Clifford Wolf	2018-01-05	2	-2/+2
\|/ \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Bugfix in verilog_defaults argument parser	Clifford Wolf	2017-12-24	1	-1/+1
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*	Add support for Verific PRIM_SVA_NOT properties	Clifford Wolf	2017-12-10	1	-10/+25
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*	Add Verific OPER_SVA_STABLE support	Clifford Wolf	2017-12-10	1	-2/+32
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*	Refactoring Verific SVA rewriter	Clifford Wolf	2017-12-10	1	-62/+70
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*	Fix error handling for nested always/initial	Clifford Wolf	2017-12-02	2	-0/+5
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*	Add Verilog "automatic" keyword (ignored in synthesis)	Clifford Wolf	2017-11-23	2	-13/+18
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*	Accept real-valued delay values	Clifford Wolf	2017-11-18	1	-0/+1
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*	Accommodate Windows-style paths during include-file processing.	William D. Jones	2017-11-14	1	-4/+20
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*	Remove vhdl2verilog	Clifford Wolf	2017-10-25	2	-184/+0
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*	Remove all PSL support code from verific.cc	Clifford Wolf	2017-10-20	1	-179/+17
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*	Add "verific -vlog-libdir"	Clifford Wolf	2017-10-13	1	-0/+12
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*	Add "verific -vlog-incdir" and "verific -vlog-define"	Clifford Wolf	2017-10-13	1	-0/+35
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*	Update Verific README	Clifford Wolf	2017-10-13	1	-0/+7
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*	Add Verific fairness/liveness support	Clifford Wolf	2017-10-12	1	-11/+32
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2017-10-10	1	-16/+5
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\| *	Remove some dead code	Clifford Wolf	2017-10-10	1	-15/+0
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\| *	Allow $past, $stable, $rose, $fell in $global_clock blocks	Clifford Wolf	2017-10-10	1	-1/+5
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* \|	Start work on pre-processor for Verific SVA properties	Clifford Wolf	2017-10-10	1	-10/+153
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*	Improve handling of Verific errors	Clifford Wolf	2017-10-05	1	-11/+9
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*	Improve Verific error handling, check VHDL static asserts	Clifford Wolf	2017-10-04	1	-11/+25
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*	Fix nasty bug in Verific bindings	Clifford Wolf	2017-10-04	1	-1/+1
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*	Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys	Clifford Wolf	2017-10-03	2	-14/+14
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\| *	Turned a few member functions into const, esp. dumpAst(), dumpVlog().	Udi Finkelstein	2017-09-30	2	-14/+14
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* \|	Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the ↵	Udi Finkelstein	2017-09-30	1	-3/+5
\|/ \| \| \| \| \|	textbook solution (Oreilly 'Flex & Bison' page 189)
*	Allow $size and $bits in verilog mode, actually check test case	Clifford Wolf	2017-09-29	1	-1/+1
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*	$size() now works correctly for all cases!	Udi Finkelstein	2017-09-26	1	-17/+17
\| \| \| \|	It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
*	$size() seems to work now with or without the optional parameter.	Udi Finkelstein	2017-09-26	1	-10/+40
\| \| \| \|	Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
*	enable $bits() and $size() functions only when the SystemVerilog flag is ↵	Udi Finkelstein	2017-09-26	1	-1/+1
\| \| \| \|	enabled for read_verilog
*	Added $bits() for memories as well.	Udi Finkelstein	2017-09-26	1	-2/+26
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*	$size() now works with memories as well!	Udi Finkelstein	2017-09-26	1	-1/+3
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*	Add $size() function. At the moment it works only on expressions, not on ↵	Udi Finkelstein	2017-09-26	1	-0/+14
\| \| \| \|	memories.
*	Increase maximum LUT size in blifparse to 12 bits	Clifford Wolf	2017-09-27	1	-1/+1
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