aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/verilog
Commit message (Collapse)AuthorAgeFilesLines
...
* | | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
|/ / | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Merge branch 'master' into wandworStefan Biereigel2019-05-272-9/+19
|\ \
| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-272-9/+19
| | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel
* | | fix indentation across filesStefan Biereigel2019-05-231-2/+2
| | |
* | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-232-1/+9
|/ /
* | Read bigger Verilog files.Kaj Tuomi2019-05-181-1/+1
| | | | | | | | Hit parser limit with 3M gate design. This commit fix it.
* | Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-161-2/+2
|\ \ | | | | | | Support for attributes on parameters and localparams for Verilog frontend
| * | Added support for parsing attributes on parameters in Verilog frontent. ↵Maciej Kurc2019-05-161-2/+2
| | | | | | | | | | | | | | | | | | Content of those attributes is ignored. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-141-1/+9
|/ /
* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-064-33/+328
|\ \ | | | | | | Add specify parser
| * \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-062-2/+10
| |\ \
| * \ \ Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-2/+2
| |\ \ \ | | | |/ | | |/|
| * | | Improve $specrule interfaceClifford Wolf2019-04-232-9/+19
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-232-2/+78
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add specify parserClifford Wolf2019-04-234-33/+243
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of Bison 2.6, name-prefix is deprecated. This fixes frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated] %name-prefix "frontend_verilog_yy" For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html Compile tested only. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* | | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-042-1/+5
|\ \ \ | | | | | | | | Add approximate support for SV "var" keyword
| * | | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-042-1/+5
| | |/ | |/| | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / | Add support for SVA "final" keywordClifford Wolf2019-05-042-1/+5
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / Include filename in "Executing Verilog-2005 frontend" message, fixes #959Clifford Wolf2019-04-301-2/+2
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* New behavior for front-end handling of whiteboxesClifford Wolf2019-04-203-16/+30
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-183-7/+20
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906Clifford Wolf2019-03-291-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-211-5/+24
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-102-92/+66
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Also add support for labels on sva module items, fixes #699Clifford Wolf2019-03-082-44/+113
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for SVA labels in read_verilogClifford Wolf2019-03-071-23/+79
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-3/+3
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
| | | | | | Fixes #737 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵Udi Finkelstein2018-10-251-14/+14
| | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-182-0/+88
|\ | | | | Support for SystemVerilog interfaces and modports
| * Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
| |
| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+21
| |
| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-122-0/+68
| | | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | ignore protect endprotectargama2018-10-161-0/+3
|/
* Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-243-6/+49
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵Clifford Wolf2018-09-231-3/+9
| | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "make coverage"Clifford Wolf2018-08-273-6/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #610 from udif/udif_specify_round2Clifford Wolf2018-08-231-16/+39
|\ | | | | More specify/endspecify fixes
| * Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| | | | | | | | | | Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
| * Yosys can now parse ↵Udi Finkelstein2018-08-201-10/+22
| | | | | | | | | | | | | | https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value.
| * A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
| | | | | | | | Just remember specify blocks are parsed but ignored.
* | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-231-1/+9
|/ | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-09 09:15:40 +0000