| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | Implemented proper handling of stub placeholder modules | Clifford Wolf | 2013-03-28 | 1 | -1/+9 | |
| * | Added mem2reg option to verilog frontend | Clifford Wolf | 2013-03-24 | 1 | -1/+11 | |
| * | Added help messages to ilang and verilog frontends | Clifford Wolf | 2013-03-01 | 1 | -1/+46 | |
| * | Moved stand-alone libs to libs/ directory and added libs/subcircuit | Clifford Wolf | 2013-02-27 | 1 | -1/+1 | |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+148 | |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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