| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 3 | -5/+68 | |
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| | * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 4 | -14/+175 | |
| | | | | | | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
| * | | Merge pull request #638 from udif/pr_reg_wire_error | Clifford Wolf | 2018-10-17 | 1 | -0/+12 | |
| |\ \ | |/ |/| | Fix issue #630 | |||||
| | * | Fixed issue #630 by fixing a minor typo in the previous commit | Udi Finkelstein | 2018-09-25 | 1 | -2/+2 | |
| | | | | | | | | | (as well as a non critical minor code optimization) | |||||
| | * | Merge branch 'master' into pr_reg_wire_error | Udi Finkelstein | 2018-09-18 | 4 | -237/+254 | |
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| | * | | Fixed remaining cases where we check fo wire reg/wire incorrect assignments | Udi Finkelstein | 2018-09-18 | 1 | -0/+12 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule | |||||
| * | | | Fix for issue 594. | Tom Verbeure | 2018-10-02 | 1 | -1/+2 | |
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| * | | | Add read_verilog $changed support | Dan Gisselquist | 2018-10-01 | 1 | -1/+4 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Fix handling of $past 2nd argument in read_verilog | Clifford Wolf | 2018-09-30 | 1 | -1/+1 | |
| | |/ |/| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 2 | -8/+11 | |
| | | | | | | | | | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same. | |||||
| * | | Merge pull request #591 from hzeller/virtual-override | Clifford Wolf | 2018-08-15 | 1 | -4/+4 | |
| |\ \ | | | | | | | Consistent use of 'override' for virtual methods in derived classes. | |||||
| | * | | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -4/+4 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | |||||
| * | | | Merge pull request #590 from hzeller/remaining-file-error | Clifford Wolf | 2018-08-15 | 1 | -15/+15 | |
| |\ \ \ | | | | | | | | | Fix remaining log_file_error(); emit dependent file references in new… | |||||
| | * | | | Fix remaining log_file_error(); emit dependent file references in new line. | Henner Zeller | 2018-07-20 | 1 | -15/+15 | |
| | |/ / | | | | | | | | | | | | | | | | | | | There are some places that reference dependent file locations ("this function was called from ..."). These are now in a separate line for ease of jumping to it with the editor (behaves similarly to compilers that emit dependent messages). | |||||
| * | | | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 3 | -2/+50 | |
| |\ \ \ | |/ / |/| / | |/ | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | |||||
| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 3 | -7/+40 | |
| | | | | | | | | | No longer false warnings for memories and assertions | |||||
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 3 | -2/+17 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | |||||
| * | | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 3 | -132/+128 | |
| | | | | | | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion. | |||||
| * | | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 2 | -77/+76 | |
| | | | | | | | | | Wherever we can report a source-level location. | |||||
| * | | Provide source-location logging. | Henner Zeller | 2018-07-19 | 1 | -3/+2 | |
| | | | | | | | | | | | | | | | | | o Provide log_file_warning() and log_file_error() that prefix the log message with <filename>:<lineno>: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil. | |||||
| * | | Fix handling of signed memories | Clifford Wolf | 2018-06-28 | 1 | -0/+3 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add (* gclk *) attribute support | Clifford Wolf | 2018-06-01 | 1 | -0/+9 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 2 | -6/+14 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 2 | -3/+3 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 1 | -0/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 2 | -2/+2 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix error handling for nested always/initial | Clifford Wolf | 2017-12-02 | 2 | -0/+5 | |
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| * | Remove some dead code | Clifford Wolf | 2017-10-10 | 1 | -15/+0 | |
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| * | Allow $past, $stable, $rose, $fell in $global_clock blocks | Clifford Wolf | 2017-10-10 | 1 | -1/+5 | |
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| * | Turned a few member functions into const, esp. dumpAst(), dumpVlog(). | Udi Finkelstein | 2017-09-30 | 2 | -14/+14 | |
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| * | Allow $size and $bits in verilog mode, actually check test case | Clifford Wolf | 2017-09-29 | 1 | -1/+1 | |
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| * | $size() now works correctly for all cases! | Udi Finkelstein | 2017-09-26 | 1 | -17/+17 | |
| | | | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly. | |||||
| * | $size() seems to work now with or without the optional parameter. | Udi Finkelstein | 2017-09-26 | 1 | -10/+40 | |
| | | | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated. | |||||
| * | enable $bits() and $size() functions only when the SystemVerilog flag is ↵ | Udi Finkelstein | 2017-09-26 | 1 | -1/+1 | |
| | | | | | enabled for read_verilog | |||||
| * | Added $bits() for memories as well. | Udi Finkelstein | 2017-09-26 | 1 | -2/+26 | |
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| * | $size() now works with memories as well! | Udi Finkelstein | 2017-09-26 | 1 | -1/+3 | |
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| * | Add $size() function. At the moment it works only on expressions, not on ↵ | Udi Finkelstein | 2017-09-26 | 1 | -0/+14 | |
| | | | | | memories. | |||||
| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵ | Clifford Wolf | 2017-06-07 | 1 | -0/+7 | |
| | | | | | const reg" | |||||
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 4 | -3/+12 | |
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| * | Preserve string parameters | Clifford Wolf | 2017-02-23 | 1 | -2/+8 | |
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| * | Fix incorrect "incompatible re-declaration of wire" error in tasks/functions | Clifford Wolf | 2017-02-14 | 1 | -2/+9 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 4 | -2/+6 | |
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| * | Fix bug in AstNode::mem2reg_as_needed_pass2() | Clifford Wolf | 2017-01-15 | 1 | -0/+2 | |
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| * | Fixed handling of local memories in functions | Clifford Wolf | 2017-01-05 | 1 | -2/+2 | |
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| * | Added handling of local memories and error for local decls in unnamed blocks | Clifford Wolf | 2017-01-04 | 1 | -1/+10 | |
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| * | Added Verilog $rtoi and $itor support | Clifford Wolf | 2017-01-03 | 1 | -24/+30 | |
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| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 2 | -13/+39 | |
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| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 1 | -4/+2 | |
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| * | Fixed anonymous genblock object names | Clifford Wolf | 2016-11-04 | 1 | -1/+1 | |
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| * | Some fixes in handling of signed arrays | Clifford Wolf | 2016-11-01 | 2 | -0/+7 | |
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index : iCE40/yosys | |
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