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* Fix error handling for nested always/initialClifford Wolf2017-12-022-0/+5
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* Remove some dead codeClifford Wolf2017-10-101-15/+0
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* Allow $past, $stable, $rose, $fell in $global_clock blocksClifford Wolf2017-10-101-1/+5
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* Turned a few member functions into const, esp. dumpAst(), dumpVlog().Udi Finkelstein2017-09-302-14/+14
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* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-291-1/+1
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* $size() now works correctly for all cases!Udi Finkelstein2017-09-261-17/+17
| | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
* $size() seems to work now with or without the optional parameter.Udi Finkelstein2017-09-261-10/+40
| | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
* enable $bits() and $size() functions only when the SystemVerilog flag is ↵Udi Finkelstein2017-09-261-1/+1
| | | | enabled for read_verilog
* Added $bits() for memories as well.Udi Finkelstein2017-09-261-2/+26
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* $size() now works with memories as well!Udi Finkelstein2017-09-261-1/+3
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* Add $size() function. At the moment it works only on expressions, not on ↵Udi Finkelstein2017-09-261-0/+14
| | | | memories.
* Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵Clifford Wolf2017-06-071-0/+7
| | | | const reg"
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-254-3/+12
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* Preserve string parametersClifford Wolf2017-02-231-2/+8
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* Fix incorrect "incompatible re-declaration of wire" error in tasks/functionsClifford Wolf2017-02-141-2/+9
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* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-044-2/+6
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* Fix bug in AstNode::mem2reg_as_needed_pass2()Clifford Wolf2017-01-151-0/+2
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* Fixed handling of local memories in functionsClifford Wolf2017-01-051-2/+2
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* Added handling of local memories and error for local decls in unnamed blocksClifford Wolf2017-01-041-1/+10
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* Added Verilog $rtoi and $itor supportClifford Wolf2017-01-031-24/+30
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* Added support for hierarchical defparamsClifford Wolf2016-11-152-13/+39
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* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-151-4/+2
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* Fixed anonymous genblock object namesClifford Wolf2016-11-041-1/+1
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* Some fixes in handling of signed arraysClifford Wolf2016-11-012-0/+7
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* Added avail params to ilang format, check module params in 'hierarchy -check'Clifford Wolf2016-10-221-2/+7
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* Added $anyseq cell typeClifford Wolf2016-10-142-4/+4
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* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-141-4/+11
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* Added $past, $stable, $rose, $fell SVA functionsClifford Wolf2016-09-192-2/+141
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* Added assertpmuxClifford Wolf2016-09-071-0/+1
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* Avoid creation of bogus initial blocks for assert/assume in always @*Clifford Wolf2016-09-063-1/+13
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* Added $anyconst support to yosys-smtbmcClifford Wolf2016-08-301-0/+2
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* Removed $aconst cell typeClifford Wolf2016-08-302-5/+5
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* Removed $predict againClifford Wolf2016-08-284-6/+2
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* Fixed bug with memories that do not have a down-to-zero data widthClifford Wolf2016-08-221-2/+13
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* Another bugfix in mem2reg codeClifford Wolf2016-08-213-7/+31
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* Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()Clifford Wolf2016-08-211-4/+15
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* Fixed finish_addr handling in $readmemh/$readmembClifford Wolf2016-08-201-3/+3
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* Optimize memory address port width in wreduce and memory_collect, not ↵Clifford Wolf2016-08-192-4/+13
| | | | verilog front-end
* Only allow posedge/negedge with 1 bit wide signalsClifford Wolf2016-08-101-0/+2
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* Added $anyconst and $aconstClifford Wolf2016-07-272-0/+49
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* Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-272-8/+21
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* Using $initstate in "initial assume" and "initial assert"Clifford Wolf2016-07-211-1/+6
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* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-0/+24
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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-214-6/+6
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* Added basic support for $expect cellsClifford Wolf2016-07-134-7/+16
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* Fixed mem assignment in left-hand-side concatenationClifford Wolf2016-07-081-0/+44
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* A few modifications after pull request commentsRuben Undheim2016-06-181-2/+2
| | | | | - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-183-1/+16
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* Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}Clifford Wolf2016-05-271-0/+11
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* Fixed access-after-delete bug in mem2reg codeClifford Wolf2016-05-272-6/+23
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