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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* sv: support tasks and functions within packagesZachary Snow2021-06-011-0/+20
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* Change the type of current_module to ModuleRupert Swarbrick2021-05-131-23/+25
| | | | | | | | | | | The current_module global is needed so that genRTLIL has somewhere to put cells and wires that it generates as it makes sense of expressions that it sees. However, that doesn't actually need to be an AstModule: the Module base class is enough. This patch should cause no functional change, but the point is that it's now possible to call genRTLIL with a module that isn't an AstModule as "current_module". This will be needed for 'bind' support.
* Use range-based for loop in AST::processRupert Swarbrick2021-05-131-21/+21
| | | | | | No functional change: just get rid of the explicit iterator and replace (*it)-> with child->. It's even the same number of characters, but is hopefully a little easier to read.
* ast: make design available to process_module()Zachary Snow2021-03-241-8/+8
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* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-2/+25
| | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme.
* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-121-1/+0
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+2
| | | | | | It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters.
* Merge pull request #2643 from zachjs/fix-param-no-default-logwhitequark2021-03-081-1/+1
|\ | | | | Fix param without default log line
| * Fix param without default log lineZachary Snow2021-03-071-1/+1
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* | verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-081-0/+2
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* Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-071-2/+27
|\ | | | | sv: support for parameters without default values
| * sv: support for parameters without default valuesZachary Snow2021-03-021-2/+27
| | | | | | | | | | | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* | sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-061-0/+2
|/ | | | | | - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
* frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-231-8/+16
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* ast: fix dump_vlog display of casex/casezMarcelina Kościelnicka2021-01-291-2/+2
| | | | | | The first child of AST_CASE is the case expression, it's subsequent childrean that are AST_COND* and can be used to discriminate the type of the case.
* Return correct modname when found in cache.Julius Roob2020-11-261-0/+1
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* Added $high(), $low(), $left(), $right()Udi Finkelstein2020-09-151-0/+6
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* static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+1
| | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* Generalise structs and add support for packed unions.Peter Crozier2020-05-121-0/+1
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* Implement SV structs.Peter Crozier2020-05-081-0/+2
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* Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-0/+2
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-021-0/+4
| | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Clear current_scope when done with RTLIL generation, fixes #1837Claire Wolf2020-04-221-0/+4
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-2/+0
| | | | Fixes #1819, #1820.
* Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-211-0/+5
|\ | | | | Improved rewrite code for writing to bit slice
| * Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-161-0/+5
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-181-0/+3
| | | | | | | | | | | | | | | | | | | | The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute.
* | ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-161-0/+2
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-34/+34
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* kernel: use more ID::*Eddie Hung2020-04-021-6/+6
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-33/+39
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-181-33/+39
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* | Merge pull request #1783 from boqwxp/astcc_cleanupEddie Hung2020-03-301-13/+20
|\ \ | | | | | | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
| * | Add explanatory comment about inefficient wire removal and remove ↵Alberto Gonzalez2020-03-301-4/+8
| | | | | | | | | | | | | | | | | | superfluous call to `fixup_ports()`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | Revert over-aggressive change to a more modest cleanup.Alberto Gonzalez2020-03-271-2/+3
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| * | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.Alberto Gonzalez2020-03-191-11/+13
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* / Simplify was not being called for packages. Broke typedef enums.Peter Crozier2020-03-221-5/+8
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* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-32/+14
|\ | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-32/+14
| | | | | | | | and RTLIL nodes.
* | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-271-11/+19
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* add attributes for enumerated values in ilangJeff Wang2020-02-171-0/+1
| | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
* partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-3/+20
| | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-141-0/+3
|\ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-0/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix for svinterfacesEddie Hung2019-09-301-2/+8
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* | module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-301-32/+50
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* Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵Clifford Wolf2019-09-201-18/+29
| | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove newlineEddie Hung2019-08-291-1/+0
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* Restore non-deferred code, deferred case to ignore non constant attrEddie Hung2019-08-291-5/+12
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