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* Use C++11 final/override keywords.whitequark2020-06-181-1/+1
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* kernel: use more ID::*Eddie Hung2020-04-021-2/+2
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* Add support for optimizing exists-forall problems.Alberto Gonzalez2020-03-132-2/+22
| | | | | | Modifies smt2 backend to recognize `$anyconst` etc. assigned to a wire with the `maximize` or `minimize` attribute and emit `; yosys-smt2-maximize` or `; yosys-smt2-minimize` directives as appropriate. Modifies `backends/smt2/smtbmc.py` and `smtio.py` to recognize those directives and emit a `(maximize ...)` or `(minimize ...)` command at the end of `smt_forall_assert()`, as described in the paper "νZ - An Optimizing SMT Solver" by Nikolaj Bjørner et al. Adds an example `examples/smtbmc/demo9.v` to show how it can be used.
* set undriven pads to zeroPepijn de Vos2019-09-041-2/+2
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* fix tcl scriptPepijn de Vos2019-09-041-2/+1
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* add broken TCL run scriptPepijn de Vos2019-09-042-0/+18
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* Add demonstration of breakagePepijn de Vos2019-09-041-0/+1
| | | | Unused outputs lead to undriven buffers, which lead to syntax errors.
* Update example for GW1NR-9Pepijn de Vos2019-09-044-47/+28
| | | | This uses the Trenz TEC0117 on Gowin IDE 1.8.4
* Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-131-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
* Add a simple example for Spartan 6Marcin Kościelnicki2019-07-245-0/+47
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* Added cell_stats exampleBenedikt Tutzer2019-04-034-478/+54
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* Merge remote-tracking branch 'origin/master' into feature/python_bindingsBenedikt Tutzer2019-03-2816-1/+215
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| * Merge pull request #856 from kprasadvnsi/masterClifford Wolf2019-03-076-10/+12
| |\ | | | | | | examples/anlogic/ now also output the SVF file.
| | * examples/anlogic/ now also output the SVF file.Kali Prasad2019-03-066-10/+12
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| * | Refactor SF2 iobuf insertion, Add clkint insertionClifford Wolf2019-03-061-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve igloo2 exampleClifford Wolf2019-03-051-2/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve igloo2 exampleClifford Wolf2019-03-052-2/+54
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improvements in SF2 flow and demoClifford Wolf2019-03-052-1/+2
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve igloo2 exmapleClifford Wolf2019-03-054-8/+16
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add missing newlineClifford Wolf2019-03-051-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Added examples/anlogic/Kali Prasad2019-03-047-0/+55
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| * Improve igloo2 exampleClifford Wolf2019-03-032-3/+10
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Update igloo2 example to Libero v12.0Clifford Wolf2019-03-032-6/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Cleanups in igloo2 example designClifford Wolf2019-01-176-7/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add SF2 IO buffer insertionClifford Wolf2019-01-172-2/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve Igloo2 exampleClifford Wolf2019-01-178-22/+41
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve igloo2 exampleClifford Wolf2019-01-084-5/+29
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add skeleton Yosys-Libero igloo2 example projectClifford Wolf2019-01-055-0/+44
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-151-1/+1
| |\ | | | | | | Consistent use of 'override' for virtual methods in derived classes.
| | * Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
| * | fix basys3 examplejapm482018-07-222-0/+4
| |/ | | | | | | | | | | | | Added `CONFIG_VOLTAGE` and `CFGBVS` to constraints file to avoid warning `DRC 23-20`. Added `open_hw` needed for programming.
* / Added sample code for python-apiBenedikt Tutzer2018-12-113-0/+479
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* Update examples/cmos/counter.ys to use "synth" commandClifford Wolf2018-05-301-5/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add smtbmc support for exist-forall problemsClifford Wolf2018-02-233-2/+23
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixed the -vout flag to -vqm in examples/intel directorydh732017-11-144-4/+4
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* Add timing constraints to osu035 exampleClifford Wolf2017-10-103-2/+4
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* Add examples/osu035Clifford Wolf2017-05-234-0/+30
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* Replace CRLF line endings with LF in de2i.qsf (quartus example)Clifford Wolf2017-04-121-1098/+1098
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* Squelch trailing whitespaceLarry Doolittle2017-04-126-31/+31
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* Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAsdh732017-04-0517-0/+1287
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* Added $assert/$assume support to AIGER back-endClifford Wolf2016-12-032-3/+3
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* Added examples/aiger/Clifford Wolf2016-12-014-0/+53
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* Progress in examples/gowin/Clifford Wolf2016-11-085-21/+95
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* Added examples/gowin/Clifford Wolf2016-11-076-0/+57
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* Added $anyseq cell typeClifford Wolf2016-10-141-1/+2
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* yosys-smtbmc meminit supportClifford Wolf2016-09-083-2/+29
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* Improvements in assertpmuxClifford Wolf2016-09-073-2/+25
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* Made examples/smtbmc/demo1.v more interestingClifford Wolf2016-09-021-1/+1
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* Added $anyconst support to yosys-smtbmcClifford Wolf2016-08-303-1/+29
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