| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | smt2: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -186/+244 | |
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| * | | verilog_backend: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -274/+251 | |
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| * | | smtbmc: escape identifiers in verilog testbench | Jakob Wenzel | 2020-10-06 | 1 | -11/+29 | |
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| * | | write_verilog: emit intermediate wire for constant values in sensitivity list | N. Engelhardt | 2020-09-28 | 1 | -7/+53 | |
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| * | | Merge pull request #2372 from nakengelhardt/name_is_public | N. Engelhardt | 2020-09-21 | 4 | -8/+8 | |
| |\ \ | | | | | | | add IdString::isPublic() | |||||
| | * | | use the new isPublic() in a few places | N. Engelhardt | 2020-09-14 | 4 | -8/+8 | |
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| * | | | Merge pull request #2369 from Xiretza/gitignores | Miodrag Milanović | 2020-09-10 | 2 | -0/+2 | |
| |\ \ \ | |/ / |/| | | Add missing gitignores for test artifacts | |||||
| | * | | Add missing gitignores for test artifacts | Xiretza | 2020-08-31 | 2 | -0/+2 | |
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| * | | | cxxrtl: expose driver kind in debug information. | whitequark | 2020-09-02 | 3 | -12/+112 | |
| | | | | | | | | | | | | | | | | | | | This can be useful to determine whether the wire should be a part of a design checkpoint, whether it can be used to override design state, and whether driving it may cause a conflict. | |||||
| * | | | cxxrtl: improve handling of FFs with async inputs (other than CLK). | whitequark | 2020-09-02 | 1 | -22/+23 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, the meaning of "sync def" included some flip-flop cells but not others. There was no actual reason for this; it was just poorly defined. After this commit, a "sync def" means that a wire holds design state because it is connected directly to a flip-flop output, and may never be unbuffered. This is not affected by presence of async inputs. | |||||
| * | | | cxxrtl: expose port direction in debug information. | whitequark | 2020-09-02 | 3 | -5/+51 | |
| | | | | | | | | | | | | | | | | | | | This can be useful to distinguish e.g. a combinatorially driven wire with type `CXXRTL_VALUE` from a module input with the same type, as well as general introspection. | |||||
| * | | | cxxrtl: fix typo in comment. NFC. | whitequark | 2020-09-02 | 1 | -1/+1 | |
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| * | | | cxxrtl: fix inaccuracy in CXXRTL_ALIAS documentation. NFC. | whitequark | 2020-09-02 | 1 | -1/+1 | |
| |/ / | | | | | | | | | Nodes driven by a constant value have type CXXRTL_VALUE and their `next` pointer set to NULL. (This is already documented.) | |||||
| * | | write_smt2: fix SMT-LIB tutorial URL | whitequark | 2020-08-29 | 1 | -1/+1 | |
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| * | | Replace "ILANG" with "RTLIL" everywhere. | whitequark | 2020-08-26 | 5 | -34/+49 | |
| | | | | | | | | | | | | | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility. | |||||
| * | | Ensure smt2 comments are associated with accessors | Noah Moroze | 2020-08-20 | 1 | -9/+20 | |
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| * | | Respect \A_SIGNED for $shift | Xiretza | 2020-08-18 | 3 | -17/+23 | |
| | | | | | | | | | | | | | This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits). | |||||
| * | | cxxrtl.h: Fix incorrect CarryOut in alu() | Andy Knowles | 2020-08-12 | 1 | -8/+3 | |
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| * | | cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False | Andy Knowles | 2020-08-12 | 1 | -2/+8 | |
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| * | | verilog_backend: Add handling for all FF types. | Marcelina Kościelnicka | 2020-07-30 | 1 | -252/+134 | |
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| * | smtio: Emit `mode: start` options before `set-logic` command and any other ↵ | Alberto Gonzalez | 2020-07-20 | 1 | -1/+8 | |
| | | | | | | | options after it. Refer to the SMT-LIB specification, section 4.1.7. According to the spec, some options can only be specified in `start` mode. Once the solver sees `set-logic`, it moves to `assert` mode. | |||||
| * | smtio: Add support for parsing `yosys-smt2-solver-option` info statements. | Alberto Gonzalez | 2020-07-20 | 1 | -3/+10 | |
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| * | smt2: Add `-solver-option` option. | Alberto Gonzalez | 2020-07-20 | 1 | -0/+13 | |
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| * | Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc | Claire Wolf | 2020-07-20 | 2 | -4/+4 | |
| | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
| * | Merge pull request #2273 from whitequark/write-verilog-always-star-initial | clairexen | 2020-07-16 | 1 | -0/+5 | |
| |\ | | | | | verilog_backend: in non-SV mode, add a trigger for `always @*` | |||||
| | * | verilog_backend: in non-SV mode, add a trigger for `always @*`. | whitequark | 2020-07-16 | 1 | -0/+5 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit only affects translation of RTLIL processes (for which there is limited support). Due to the event-driven nature of Verilog, processes like reg x; always @* x <= 1; may never execute. This can be fixed in SystemVerilog code by using `always_comb` instead of `always @*`, but in Verilog-2001 the options are limited. This commit implements the following workaround: reg init = 0; reg x; always @* begin if (init) begin end x <= 1; end Fixes #2271. | |||||
| * | | Merge pull request #2272 from whitequark/write-verilog-sv | clairexen | 2020-07-16 | 1 | -11/+18 | |
| |\| | | | | | verilog_backend: add `-sv` option, make `-o <filename>.sv` work | |||||
| | * | verilog_backend: add `-sv` option, make `-o <filename>.sv` work. | whitequark | 2020-07-16 | 1 | -11/+18 | |
| | | | | | | | | | See #2271. | |||||
| * | | cxxrtl: fix typo. NFC. | whitequark | 2020-07-14 | 1 | -1/+1 | |
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| * | cxxrtl: expose eval() and commit() via the C API. | whitequark | 2020-07-12 | 2 | -0/+20 | |
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| * | cxxrtl: add missing extern "C". | whitequark | 2020-07-09 | 1 | -0/+1 | |
| | | | | | This bug was hidden if a header was generated. | |||||
| * | cxxrtl: update help text. | whitequark | 2020-06-26 | 1 | -2/+2 | |
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| * | Merge pull request #2168 from whitequark/assert-unused-exprs | clairexen | 2020-06-25 | 1 | -2/+0 | |
| |\ | | | | | Use (and ignore) the expression provided to log_assert in NDEBUG builds | |||||
| | * | Use (and ignore) the expression provided to log_assert in NDEBUG builds. | whitequark | 2020-06-19 | 1 | -2/+0 | |
| | | | | | | | | | | | This avoids warnings in NDEBUG builds emitted when a variable is only used in log_assert, but is always defined. | |||||
| * | | cxxrtl: Add support for the new FF types. | Marcelina Kościelnicka | 2020-06-24 | 1 | -5/+22 | |
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| * | Merge pull request #2173 from whitequark/use-cxx11-final-override | whitequark | 2020-06-19 | 17 | -40/+40 | |
| |\ | | | | | Use C++11 final/override/[[noreturn]] | |||||
| | * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 17 | -40/+40 | |
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| * | | cxxrtl: add .get() and .set() accessors on value<> and wire<>. | whitequark | 2020-06-19 | 1 | -6/+47 | |
| |/ | | | | | | | | | | | | | For several reasons: * They're more convenient than accessing .data. * They accommodate variably-sized types like size_t transparently. * They statically ensure that no out of range conversions happen. For now these are only provided for unsigned integers, but eventually they should be provided for signed integers too. (Annoyingly this affects conversions to/from `char` at the moment.) Fixes #2127. | |||||
| * | Merge pull request #2167 from whitequark/cxxrtl-fix-ndebug | whitequark | 2020-06-18 | 1 | -1/+2 | |
| |\ | | | | | cxxrtl: don't compute vital values in log_assert() | |||||
| | * | cxxrtl: don't compute vital values in log_assert(). | whitequark | 2020-06-17 | 1 | -1/+2 | |
| | | | | | | | | | | | | | This breaks NDEBUG builds. Fixes #2166. | |||||
| * | | Merge pull request #2163 from jfng/cxxrtl-blackbox-debuginfo | whitequark | 2020-06-17 | 1 | -13/+17 | |
| |\ \ | | | | | | | cxxrtl: restrict the debug info of a blackbox to its ports. | |||||
| | * | | cxxrtl: restrict the debug info of a blackbox to its ports. | Jean-François Nguyen | 2020-06-16 | 1 | -13/+17 | |
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| * | | Merge pull request #2160 from whitequark/cxxrtl-fix-warning | whitequark | 2020-06-17 | 1 | -21/+23 | |
| |\ \ | |/ |/| | cxxrtl: avoid unused variable warning for transparent $memrd ports | |||||
| | * | cxxrtl: avoid unused variable warning for transparent $memrd ports. NFC. | whitequark | 2020-06-15 | 1 | -21/+23 | |
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| * | | Merge pull request #2159 from MerryMage/cxxrtl-mul | whitequark | 2020-06-15 | 1 | -17/+22 | |
| |\ \ | |/ |/| | cxxrtl: Implement chunk-wise multiplication | |||||
| | * | cxxrtl: Implement chunk-wise multiplication | MerryMage | 2020-06-15 | 1 | -17/+22 | |
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| * | | Merge pull request #2158 from miek/sshr-sign-extension | whitequark | 2020-06-15 | 1 | -2/+4 | |
| |\ \ | |/ |/| | cxxrtl: fix sshr sign-extension. | |||||
| | * | cxxrtl: fix sshr sign-extension. | Mike Walters | 2020-06-15 | 1 | -2/+4 | |
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| * | | Merge pull request #2151 from whitequark/cxxrtl-fix-rzext | whitequark | 2020-06-13 | 1 | -2/+2 | |
| |\ \ | |/ |/| | cxxrtl: fix rzext() | |||||
| | * | cxxrtl: fix rzext(). | whitequark | 2020-06-13 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | This was a correctness issue, but one of the consequences is that it resulted in jumps in generated machine code where there should have been none. As a side effect of fixing the bug, Minerva SoC became 10% faster. | |||||
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index : iCE40/yosys | |
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