| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | metadata -> jny: migrated to the proper name for the pass | Aki Van Ness | 2022-04-08 | 3 | -21/+19 | |
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| * | pass metadata: added the machinery to write param and attributes | Aki Van Ness | 2022-04-08 | 1 | -8/+27 | |
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| * | pass metadata: removed superfluous `stringf` calls | Aki Van Ness | 2022-04-08 | 1 | -37/+40 | |
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| * | pass metadata: some more rough work on dumping the parameters and attributes | Aki Van Ness | 2022-04-08 | 1 | -6/+6 | |
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| * | pass metadata: fixed the MetadataWriter object initializer so GCC 4.8 is happy | Aki Van Ness | 2022-04-08 | 1 | -1/+1 | |
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| * | pass metadata: added the output of parameters, | Aki Van Ness | 2022-04-08 | 1 | -7/+35 | |
| | | | | | it's kinda dumb at the moment and needs parsing based on type but it's a start | |||||
| * | pass metadata: fixed some of the output formatting | Aki Van Ness | 2022-04-08 | 1 | -0/+3 | |
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| * | pass metadata: initial commit of the metadata pass for exporting design ↵ | Aki Van Ness | 2022-04-08 | 2 | -0/+277 | |
| | | | | | metadata for yosys assisted tooling | |||||
| * | smtbmc: fix bmc with no assertions | Jannis Harder | 2022-03-29 | 1 | -0/+2 | |
| | | | | | this was broken by the `--keep-going` changes | |||||
| * | Merge pull request #3253 from jix/smtbmc-nodeepcopy | Jannis Harder | 2022-03-28 | 1 | -6/+6 | |
| |\ | | | | | smtbmc: Avoid unnecessary deep copies during unrolling | |||||
| | * | smtbmc: Avoid unnecessary deep copies during unrolling | Jannis Harder | 2022-03-28 | 1 | -6/+6 | |
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| * | | Merge pull request #3247 from jix/smtbmc-keepgoing | Jannis Harder | 2022-03-28 | 1 | -50/+143 | |
| |\ \ | |/ |/| | smtbmc `--keep-going` | |||||
| | * | yosys-smtbmc: Option to keep going after failed assertions in BMC mode | Jannis Harder | 2022-03-24 | 1 | -48/+141 | |
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| | * | yosys-smtbmc: Fix typo in help text, remove trailing whitespace | Jannis Harder | 2022-03-24 | 1 | -2/+2 | |
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| * | | Add -no-startoffset option to write_aiger | Miodrag Milanovic | 2022-03-25 | 1 | -8/+17 | |
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| * | | ignore # comment lines | N. Engelhardt | 2022-03-24 | 1 | -1/+1 | |
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| * | Merge pull request #3226 from YosysHQ/micko/btor2witness | Miodrag Milanović | 2022-03-11 | 1 | -2/+2 | |
| |\ | | | | | Sim support for btor2 witness files | |||||
| | * | Fix handling of some formal cells in btor back-end | Claire Xenia Wolf | 2022-03-11 | 1 | -6/+2 | |
| | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| | * | handle state names of $anyconst and $anyseq | Miodrag Milanovic | 2022-03-11 | 1 | -1/+5 | |
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| * | | Merge pull request #3210 from rqou/json-signed | Miodrag Milanović | 2022-03-07 | 1 | -0/+2 | |
| |\ \ | |/ |/| | json: Add help message for `signed` field | |||||
| | * | json: Add help message for `signed` field | R | 2022-02-21 | 1 | -0/+2 | |
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| * | | Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_id | Miodrag Milanović | 2022-03-04 | 2 | -4/+12 | |
| |\ \ | | | | | | | add argument for printing cell names in yosys-smtbmc | |||||
| | * | | print cell name for properties in yosys-smtbmc | N. Engelhardt | 2022-02-22 | 2 | -4/+12 | |
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| * | | Merge pull request #3207 from nakengelhardt/json_escape_quotes | Miodrag Milanović | 2022-03-04 | 1 | -1/+16 | |
| |\ \ | | | | | | | fix handling of escaped chars in json backend and frontend (mostly) | |||||
| | * | | fix handling of escaped chars in json backend and frontend | N. Engelhardt | 2022-02-18 | 1 | -1/+16 | |
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| * / | Add a bit of flexibilty re trace length when processing aiger witnesses in ↵ | Claire Xenia Wolf | 2022-02-11 | 1 | -1/+4 | |
| |/ | | | | | | smtbmc.py Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| * | verilog backend: Emit a `wire` for ports as well. | Marcelina Kościelnicka | 2022-01-31 | 1 | -1/+1 | |
| | | | | | Fixes #3177. | |||||
| * | Add $bmux and $demux cells. | Marcelina Kościelnicka | 2022-01-28 | 7 | -2/+77 | |
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| * | cxxrtl: don't reset elided wires with \init attribute. | Catherine | 2021-12-25 | 1 | -0/+2 | |
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| * | cxxrtl: demote wires not inlinable only in debug_eval to locals. | Catherine | 2021-12-15 | 1 | -3/+4 | |
| | | | | | | | Fixes #3112. Co-authored-by: Irides <irides@irides.network> | |||||
| * | Add clean_zerowidth pass, use it for Verilog output. | Marcelina Kościelnicka | 2021-12-12 | 1 | -0/+2 | |
| | | | | | | | | This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103. | |||||
| * | Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2 | Catherine | 2021-12-12 | 2 | -108/+80 | |
| |\ | | | | | cxxrtl: preserve interior memory pointers across reset | |||||
| | * | cxxrtl: preserve interior memory pointers across reset. | Catherine | 2021-12-11 | 2 | -95/+67 | |
| | | | | | | | | | | | | | | | | | Before this commit, values, wires, and memories with an initializer were value-initialized in emitted C++ code. After this commit, all values, wires, and memories are default-initialized, and the default constructor of generated modules calls the reset() method, which assigns the members that have an initializer. | |||||
| | * | cxxrtl: use unique_ptr<value<>[]> to store memory contents. | whitequark | 2021-12-11 | 1 | -16/+16 | |
| | | | | | | | | | This makes the depth properly immutable. | |||||
| * | | rtlil: Dump empty connections when whole module is selected. | Marcelina Kościelnicka | 2021-12-12 | 1 | -2/+2 | |
| | | | | | | | | | | | Without this, empty connections will be always skipped by `dump`, since they contain no selected wires. This makes debugging rather confusing. | |||||
| * | | write_verilog: dump zero width sigspecs correctly. | whitequark | 2021-12-11 | 1 | -1/+2 | |
| |/ | | | | | | | | | | | | | Before this commit, zero width sigspecs were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) PR #1203 has addressed this issue before, but in an incomplete way. | |||||
| * | sta: very crude static timing analysis pass | Lofty | 2021-11-25 | 1 | -15/+16 | |
| | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com> | |||||
| * | Give initial wire unique ID, fixes #2914 | Miodrag Milanovic | 2021-11-17 | 1 | -4/+6 | |
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| * | Split module ports, 20 per line | Miodrag Milanovic | 2021-10-09 | 1 | -0/+2 | |
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| * | Hook up $aldff support in various passes. | Marcelina Kościelnicka | 2021-10-02 | 4 | -4/+19 | |
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| * | kernel/ff: Refactor FfData to enable FFs with async load. | Marcelina Kościelnicka | 2021-10-02 | 1 | -43/+70 | |
| | | | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load | |||||
| * | Add optimization to rtlil back-end for all-x parameter values | Claire Xenia Wolf | 2021-09-27 | 1 | -9/+13 | |
| | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| * | Fix protobuf backend build dependencies | the6p4c | 2021-09-17 | 1 | -0/+2 | |
| | | | | | | | | backends/protobuf/protobuf.cc depends on the source and header files generated by protoc, but this dependency wasn't explicitly declared. Add a rule to the Makefile to fix intermittent build failures when the protobuf header/source file isn't built before protobuf.cc. | |||||
| * | yosys-smtbmc: Fix reused loop variable. | Marcelina Kościelnicka | 2021-09-10 | 1 | -4/+4 | |
| | | | | | Fixes #2999. | |||||
| * | kernel/mem: Introduce transparency masks. | Marcelina Kościelnicka | 2021-08-11 | 2 | -27/+30 | |
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| * | backend/verilog: Add alternate mode for transparent read port output. | Marcelina Kościelnicka | 2021-08-01 | 1 | -1/+71 | |
| | | | | | | | This mode will be used whenever read port cannot be handled in the "extract address register" way, ie. whenever it has enable, reset, init functionality or (in the future) mixed transparency mask. | |||||
| * | backends/verilog: Support meminit with mask. | Marcelina Kościelnicka | 2021-07-28 | 1 | -3/+18 | |
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| * | Merge pull request #2885 from whitequark/cxxrtl-fix-2883 | whitequark | 2021-07-20 | 1 | -2/+8 | |
| |\ | | | | | cxxrtl: treat wires with multiple defs as not inlinable | |||||
| | * | cxxrtl: treat wires with multiple defs as not inlinable. | whitequark | 2021-07-20 | 1 | -2/+8 | |
| | | | | | | | | | Fixes #2883. | |||||
| * | | cxxrtl: treat assignable internal wires used only for debug as locals. | whitequark | 2021-07-20 | 1 | -10/+12 | |
| |/ | | | | | | This issue was introduced in commit 4aa65f40 while fixing #2739. Fixes #2882. | |||||
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index : iCE40/yosys | |
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