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| * Revert "Fold loop"Eddie Hung2019-11-271-3/+6
| * latch -> boxEddie Hung2019-11-261-1/+1
| * Fold loopEddie Hung2019-11-261-6/+3
| * Do not sigmap keep bits inside write_xaigerEddie Hung2019-11-261-1/+1
| * xaiger: do not promote output wiresEddie Hung2019-11-261-5/+0
* | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-301-2/+3
* | Really fix it!Eddie Hung2019-12-271-10/+7
* | write_xaiger: fix arrival times for non boxesEddie Hung2019-12-271-18/+25
* | write_xaiger to opt instead of just clean whiteboxesEddie Hung2019-12-231-1/+1
* | Cleanup xaiger, remove unnecessary complexity with inoutEddie Hung2019-12-171-61/+20
* | Do not sigmapEddie Hung2019-12-171-1/+1
* | Revert "Use sigmap signal"Eddie Hung2019-12-171-1/+1
* | Use sigmap signalEddie Hung2019-12-161-1/+1
* | Skip $inout transformation if not a PIEddie Hung2019-12-161-3/+5
* | Revert "write_xaiger: use sigmap bits more consistently"Eddie Hung2019-12-161-4/+5
* | write_xaiger: use sigmap bits more consistentlyEddie Hung2019-12-161-5/+4
* | Fix writing non-whole modules, including inouts and keepsEddie Hung2019-12-061-90/+81
* | write_xaiger to support part-selected modules againEddie Hung2019-12-051-11/+37
* | CleanupEddie Hung2019-12-031-11/+12
* | write_xaiger to consume abc9_init attribute for abc9_flopsEddie Hung2019-12-031-34/+28
* | Add comment, use sigmapEddie Hung2019-11-271-2/+2
* | Revert "Fold loop"Eddie Hung2019-11-271-3/+6
* | xaiger: do not promote output wiresEddie Hung2019-11-261-5/+0
* | Fold loopEddie Hung2019-11-251-6/+3
* | Do not sigmap keep bits inside write_xaigerEddie Hung2019-11-251-1/+1
* | write_xaiger back to working with whole modules onlyEddie Hung2019-11-221-5/+2
* | Revert "write_xaiger to not use module POs but only write outputs if driven"Eddie Hung2019-11-221-23/+11
* | write_xaiger to not use module POs but only write outputs if drivenEddie Hung2019-11-211-11/+23
* | abc9 to support async flops $_DFF_[NP][NP][01]_Eddie Hung2019-11-191-1/+2
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-194-21/+103
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| * write_verilog: add -extmem option, to write split memory init files.whitequark2019-11-181-10/+80
| * Use cell name for btor bad state props when it is a public nameClifford Wolf2019-11-141-9/+5
| * Add an info string symbol for bad states in btor backendMakai Mann2019-11-111-1/+10
| * Fix write_aiger bug added in 524af21Clifford Wolf2019-11-041-0/+3
| * Merge pull request #1393 from whitequark/write_verilog-avoid-initClifford Wolf2019-10-271-4/+5
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| | * write_verilog: do not print (*init*) attributes on regs.whitequark2019-09-221-4/+5
| * | Bugfix in smtio vcd handling of $-identifiersClifford Wolf2019-10-231-6/+9
* | | Rename $currQ to $abc9_currQEddie Hung2019-10-071-8/+8
* | | Get rid of latch_* in write_xaigerEddie Hung2019-10-071-7/+1
* | | Remove "write_xaiger -zinit"Eddie Hung2019-10-071-16/+6
* | | Add comment on default flop initEddie Hung2019-10-071-0/+1
* | | Get rid of output_port lookupEddie Hung2019-10-071-14/+8
* | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-051-48/+70
* | | Error if $currQ not foundEddie Hung2019-10-051-0/+4
* | | Fix merge issuesEddie Hung2019-10-041-1/+1
* | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-11/+11
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| * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-9/+9
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-032-20/+23
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| * | Change smtbmc "Warmup failed" status to "PREUNSAT"Clifford Wolf2019-10-031-14/+14
| * | Fix btor back-end to use "state" instead of "input" for undef init bitsClifford Wolf2019-10-021-6/+9
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