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* Use (and ignore) the expression provided to log_assert in NDEBUG builds.whitequark2020-06-191-2/+0
| | | | | This avoids warnings in NDEBUG builds emitted when a variable is only used in log_assert, but is always defined.
* Merge pull request #2173 from whitequark/use-cxx11-final-overridewhitequark2020-06-1917-40/+40
|\ | | | | Use C++11 final/override/[[noreturn]]
| * Use C++11 final/override keywords.whitequark2020-06-1817-40/+40
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* | cxxrtl: add .get() and .set() accessors on value<> and wire<>.whitequark2020-06-191-6/+47
|/ | | | | | | | | | | | | For several reasons: * They're more convenient than accessing .data. * They accommodate variably-sized types like size_t transparently. * They statically ensure that no out of range conversions happen. For now these are only provided for unsigned integers, but eventually they should be provided for signed integers too. (Annoyingly this affects conversions to/from `char` at the moment.) Fixes #2127.
* Merge pull request #2167 from whitequark/cxxrtl-fix-ndebugwhitequark2020-06-181-1/+2
|\ | | | | cxxrtl: don't compute vital values in log_assert()
| * cxxrtl: don't compute vital values in log_assert().whitequark2020-06-171-1/+2
| | | | | | | | | | | | This breaks NDEBUG builds. Fixes #2166.
* | Merge pull request #2163 from jfng/cxxrtl-blackbox-debuginfowhitequark2020-06-171-13/+17
|\ \ | | | | | | cxxrtl: restrict the debug info of a blackbox to its ports.
| * | cxxrtl: restrict the debug info of a blackbox to its ports.Jean-François Nguyen2020-06-161-13/+17
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* | Merge pull request #2160 from whitequark/cxxrtl-fix-warningwhitequark2020-06-171-21/+23
|\ \ | |/ |/| cxxrtl: avoid unused variable warning for transparent $memrd ports
| * cxxrtl: avoid unused variable warning for transparent $memrd ports. NFC.whitequark2020-06-151-21/+23
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* | Merge pull request #2159 from MerryMage/cxxrtl-mulwhitequark2020-06-151-17/+22
|\ \ | |/ |/| cxxrtl: Implement chunk-wise multiplication
| * cxxrtl: Implement chunk-wise multiplicationMerryMage2020-06-151-17/+22
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* | Merge pull request #2158 from miek/sshr-sign-extensionwhitequark2020-06-151-2/+4
|\ \ | |/ |/| cxxrtl: fix sshr sign-extension.
| * cxxrtl: fix sshr sign-extension.Mike Walters2020-06-151-2/+4
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* | Merge pull request #2151 from whitequark/cxxrtl-fix-rzextwhitequark2020-06-131-2/+2
|\ \ | |/ |/| cxxrtl: fix rzext()
| * cxxrtl: fix rzext().whitequark2020-06-131-2/+2
| | | | | | | | | | | | | | This was a correctness issue, but one of the consequences is that it resulted in jumps in generated machine code where there should have been none. As a side effect of fixing the bug, Minerva SoC became 10% faster.
* | Merge pull request #2145 from whitequark/cxxrtl-splitnetswhitequark2020-06-135-67/+156
|\ \ | | | | | | cxxrtl: handle multipart signals
| * | cxxrtl: handle multipart signals.whitequark2020-06-115-27/+94
| | | | | | | | | | | | This avoids losing design visibility when using the `splitnets` pass.
| * | cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.whitequark2020-06-113-40/+62
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* | | cxxrtl: always inline internal cells and slice/concat operations.whitequark2020-06-131-4/+108
| |/ |/| | | | | | | | | This can result in massive reduction in runtime, up to 50% depending on workload. Currently people are using `-mllvm -inline-threshold=` as a workaround (with clang++), but this solution is more portable.
* | cxxrtl: elide $pmux cells.whitequark2020-06-121-30/+16
| | | | | | | | | | On Minerva, this improves runtime by around 10%, mostly by ensuring that the logic driving FFs is packed into edge conditionals.
* | cxxrtl: annotate port direction as comments.whitequark2020-06-121-1/+8
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* | cxxrtl: unbuffer output wires of toplevel module.whitequark2020-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | Without unbuffering output wires of, at least, toplevel modules, it is not possible to have most designs that rely on IO via toplevel ports (as opposed to using exclusively blackboxes) converge within one delta cycle. That seriously impairs the performance of CXXRTL. This commit avoids unbuffering outputs of all modules solely so that in future, CXXRTL could gain fully separate compilation, and not for any present technical reason.
* | cxxrtl: simplify unbuffering of input wires.whitequark2020-06-121-20/+17
|/ | | | This also fixes an edge case with (*keep*) input ports.
* Merge pull request #2141 from whitequark/cxxrtl-cxx11whitequark2020-06-103-8/+10
|\ | | | | cxxrtl: various compiler compatibility fixes
| * cxxrtl: restore C++11 compatibility.whitequark2020-06-101-1/+2
| | | | | | | | This is necessary to be able to build CXXRTL models via yosys-config.
| * cxxrtl: fix a few gcc warnings.whitequark2020-06-101-5/+6
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| * Fix formatting. NFC.whitequark2020-06-101-2/+2
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* | cxxrtl: disambiguate values/wires and their aliases in debug info.whitequark2020-06-104-9/+50
|/ | | | | | | With this change, it is easier to see which signals carry state (only wire<>s appear as `reg` in VCD files) and to construct a minimal checkpoint (CXXRTL_WIRE debug items represent the canonical smallest set of state required to fully reconstruct the simulation).
* cxxrtl: allow unbuffering without localizing.whitequark2020-06-091-40/+74
| | | | | | | Although logically two separate steps, these were treated as one for historic reasons. Splitting the two makes it possible to have designs that are only 2× slower than fastest possible (and are without extra delta cycles) that allow probing all public wires.
* cxxrtl: order -On levels as localize, elide instead of the reverse.whitequark2020-06-091-8/+8
| | | | | | | | | | | Historically, elision was implemented before localization, so levels with elision are lower than corresponding levels with localization. This is unfortunate for two reasons: 1. Elision is a logical subset of localization, since it equals to not giving a name to a temporary. 2. "Localize" currently actually means "unbuffer and localize", and it would be useful to split those steps (at least for public wires) for improved design visibility.
* cxxrtl: factor out -noproc/-noflatten from -O.whitequark2020-06-091-17/+36
| | | | | | | | Although these options can be thought of as optimizations, they are essentially orthogonal to the core of -O, which is managing signal buffering and scope. Going from -O4 to -O2 means going from limited to complete design visibility, yet in both cases proc and flatten are desirable.
* cxxrtl: fix two buggy split_by functions.whitequark2020-06-092-14/+16
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* Merge pull request #2126 from whitequark/cxxrtl-non-ext-logic-opswhitequark2020-06-092-64/+35
|\ | | | | cxxrtl: ignore cell input signedness when it is irrelevant
| * cxxrtl: ignore cell input signedness when it is irrelevant.whitequark2020-06-092-64/+35
| | | | | | | | | | | | | | | | Before this commit, Verilog expressions like `x && 1` would result in references to `logic_and_us` in generated CXXRTL code, which would not compile. After this commit, since cells like that actually behave the same regardless of signedness attributes, the signedness is ignored, which also reduces the template instantiation pressure.
* | cxxrtl: add missing namespace.whitequark2020-06-091-2/+2
|/ | | | Fixes #2124.
* cxxrtl: fix format of hdlnames.whitequark2020-06-081-1/+1
| | | | | The CXXRTL code that handled the `hdlname` attribute implemented outdated semantics.
* cxxrtl: don't check immutable values for changes in VCD writer.whitequark2020-06-081-4/+10
| | | | | | | | | | | This commit changes the VCD writer such that for all signals that have `debug_item.type == VALUE && debug_item.next == nullptr`, it would only sample the value once. Commit f2d7a187 added more debug information by including constant wires, and decreased the performance of VCD writer proportionally because the constant wires were still repeatedly sampled; this commit eliminates the performance hit.
* cxxrtl: emit debug information for constant wires.whitequark2020-06-083-17/+44
| | | | | | | | | Constant wires can represent a significant chunk of the design in generic designs or after optimization. Emitting them in VCD files significantly improves usability because gtkwave removes all traces that are not present in the VCD file after reload, and iterative development suffers if switching a varying signal to a constant disrupts the workflow.
* cxxrtl: track aliases in VCD writer.whitequark2020-06-081-10/+14
| | | | | | | | | | | This commit changes the VCD writer such that for all signals that share `debug_item.curr`, it would only emit a single VCD identifier, and sample the value once. Commit 9b39c6f7 added redundancy to debug information by including alias wires, and increased the size of VCD files proportionally; this commit eliminates the redundancy from VCD files so that their size is the same as before.
* cxxrtl: emit debug information for alias wires.whitequark2020-06-081-3/+55
| | | | | | | Alias wires can represent a significant chunk of the design in highly hierarchical designs; in Minerva SRAM, there are 273 member wires and 527 alias wires. Showing them in every hierarchy level significantly improves usability.
* cxxrtl: fix typo in comment. NFC.whitequark2020-06-081-4/+4
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* cxxrtl: minor debug-related improvements.whitequark2020-06-081-2/+3
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* cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.whitequark2020-06-072-1/+1
| | | | | To avoid confusion with the C++ source files that are a part of the simulation itself and not a part of Yosys build.
* cxxrtl: add a C API for writing VCD dumps.whitequark2020-06-075-2/+204
| | | | This C API is fully featured.
* cxxrtl: only write VCD values that were actually updated.whitequark2020-06-071-10/+30
| | | | | On a representative design (Minerva SoC) this reduces VCD file size by ~20× and runtime by ~3×.
* cxxrtl: add a VCD writer using debug information.whitequark2020-06-071-0/+194
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* cxxrtl: add a C API for driving and introspecting designs.whitequark2020-06-064-29/+291
| | | | | | Compared to the C++ API, the C API currently has two limitations: 1. Memories cannot be updated in a race-free way. 2. Black boxes cannot be implemented in C.
* cxxrtl: generate debug information for non-localized public wires.whitequark2020-06-062-2/+131
| | | | | | | | | | Debug information describes values, wires, and memories with a simple C-compatible layout. It can be emitted on demand into a map, which has no runtime cost when it is unused, and allows late bound designs. The `hdlname` attribute is used as the lookup key such that original names, as emitted by the frontend, can be used for debugging and introspection.
* Merge pull request #2110 from BracketMaster/masterwhitequark2020-06-061-1/+1
|\ | | | | MacOS has even stricter stack limits in catalina.
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