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* cxxrtl: emit debug items for unused public wires.whitequark2021-07-161-3/+3
* cxxrtl: don't mark buffered internal wires as UNUSED for debug.whitequark2021-07-161-1/+1
* cxxrtl: mark dead local wires as unused even with inlining disabled.whitequark2021-07-151-4/+6
* kernel/mem: Add a coalesce_inits helper.Marcelina Kościelnicka2021-07-131-1/+5
* Add support for the Bitwuzla solverGCHQDeveloper5602021-07-121-5/+5
* cxxrtl: Support memory writes in processes.Marcelina Kościelnicka2021-07-121-6/+55
* cxxrtl: Add support for memory read port reset.Marcelina Kościelnicka2021-07-121-1/+41
* cxxrtl: Add support for mem read port initial data.Marcelina Kościelnicka2021-07-121-4/+22
* cxxrtl: Convert to Mem helpers.Marcelina Kościelnicka2021-07-121-206/+276
* Intersynth URLClaire Xenia Wolf2021-06-091-1/+1
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0819-20/+20
* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-283-19/+6
* backends/verilog: Add support for memory read port reset and init value.Marcelina Kościelnicka2021-05-271-9/+81
* backends/verilog: Add wide port support.Marcelina Kościelnicka2021-05-271-43/+88
* backends/verilog: Try to preserve mem write port priorities.Marcelina Kościelnicka2021-05-261-32/+84
* Reject wide ports in some passes that will never support them.Marcelina Kościelnicka2021-05-253-2/+21
* backend/firrtl: Convert to use Mem helpers.Marcelina Kościelnicka2021-05-241-264/+88
* btor: Use is_mem_cell in one more place.Marcelina Kościelnicka2021-05-231-1/+1
* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-223-4/+4
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-291-5/+4
* rtlil: Fix process memwr roundtrip.Marcelina Kościelnicka2021-03-231-1/+1
* json: Improve the "processes in module" message a bit.Marcelina Kościelnicka2021-03-231-1/+1
* json: Add support for memories.Marcelina Kościelnicka2021-03-151-0/+42
* Merge pull request #2642 from whitequark/cxxrtl-noproc-fixeswhitequark2021-03-111-17/+29
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| * cxxrtl: don't assert on edge sync rules tied to a constant.whitequark2021-03-071-0/+4
| * cxxrtl: allow `always` sync rules in debug_eval.whitequark2021-03-071-17/+25
* | Replace assert in xaiger with more useful error messageDan Ravensloft2021-03-101-1/+2
* | Add support for memory writes in processes.Marcelina Kościelnicka2021-03-081-3/+20
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* Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addrwhitequark2021-03-051-1/+3
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| * cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.whitequark2021-03-051-1/+3
* | Merge pull request #2634 from whitequark/cxxrtl-debug-wire-typeswhitequark2021-03-051-0/+46
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| * | cxxrtl: add pass debug flag to show assigned wire types.whitequark2021-03-051-0/+46
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* / cxxrtl: don't crash on empty designs.whitequark2021-03-051-1/+1
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* btor, smt2, smv: Add a hint on how to deal with funny FF types.Marcelina Kościelnicka2021-02-253-3/+42
* Merge pull request #2563 from whitequark/cxxrtl-msvcwhitequark2021-01-262-10/+10
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| * cxxrtl: do not use `->template` for non-dependent names.whitequark2021-01-262-10/+10
* | Improves the previous commit with a more complete coverage of the casesIris Johnson2021-01-151-12/+12
* | Handle sliced bits as clock inputs (fixes #2542)Iris Johnson2021-01-141-3/+11
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* add buffer option to spice backendPepijn de Vos2021-01-131-7/+15
* cxxrtl: don't crash generating debug information for unused wires.whitequark2020-12-221-9/+10
* cxxrtl: split processes into sync and case nodes.whitequark2020-12-221-11/+26
* cxxrtl: completely rewrite netlist layout code.whitequark2020-12-221-406/+569
* cxxrtl: simplify logic choosing wire type. NFCI.whitequark2020-12-211-19/+8
* cxxrtl: clarify node use-def construction. NFCI.whitequark2020-12-211-18/+11
* cxxrtl: fix typo.whitequark2020-12-211-2/+2
* cxxrtl: speed up bit repeats (sign extends, etc).whitequark2020-12-212-5/+28
* cxxrtl: speed up commits on clang.whitequark2020-12-211-3/+3
* cxxrtl: use `static inline` instead of `inline` in the C API.whitequark2020-12-201-1/+1
* cxxrtl: print names of cells inlined in connections.whitequark2020-12-151-1/+10
* cxxrtl: disable optimization of debug_items().whitequark2020-12-152-3/+15
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