| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -40/+40 | |
| | * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -40/+40 | |
| | * | Use log_abort() and log_assert() in BTOR backend | Clifford Wolf | 2014-03-07 | 1 | -18/+17 | |
| * | | fixed memory next issue, when same memory is written in different case statement | ahmedirfan1983 | 2014-09-18 | 1 | -8/+27 | |
| * | | added $pmux cell translation | Ahmed Irfan | 2014-09-02 | 1 | -2/+38 | |
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| * | register output corrected | Ahmed Irfan | 2014-02-11 | 1 | -1/+1 | |
| * | added concat and slice cell translation | Ahmed Irfan | 2014-02-11 | 1 | -32/+55 | |
| * | Fixed gcc compiler warnings with release build | Clifford Wolf | 2014-02-06 | 1 | -1/+1 | |
| * | Added BTOR backend README file | Clifford Wolf | 2014-02-05 | 1 | -1/+1 | |
| * | Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) | Clifford Wolf | 2014-02-03 | 1 | -0/+4 | |
| * | root bug corrected | Ahmed Irfan | 2014-01-25 | 1 | -1/+5 | |
| * | removed regex include | Ahmed Irfan | 2014-01-24 | 1 | -1/+0 | |
| * | merged clifford changes + removed regex | Ahmed Irfan | 2014-01-24 | 1 | -26/+52 | |
| * | slice bug corrected | Ahmed Irfan | 2014-01-20 | 1 | -1/+1 | |
| * | assert feature | Ahmed Irfan | 2014-01-20 | 1 | -9/+40 | |
| * | verilog default options pull | Ahmed Irfan | 2014-01-17 | 1 | -28/+97 | |
| * | slice error corrected | Ahmed Irfan | 2014-01-16 | 1 | -5/+5 | |
| * | width issues | Ahmed Irfan | 2014-01-15 | 1 | -64/+87 | |
| * | BTOR backend | Ahmed Irfan | 2014-01-14 | 1 | -274/+328 | |
| * | btor | Ahmed Irfan | 2014-01-03 | 1 | -0/+771 | |
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index : iCE40/yosys | |
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