| Commit message (Collapse) | Author | Age | Files | Lines |
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`outbit_to_cell`.
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`std::map` for `techmap_cache` and `techmap_do_cache`.
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`passes/techmap/techmap.cc`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
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blackbox: use Module::makeblackbox() method
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smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
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Co-Authored-By: clairexen <claire@symbioticeda.com>
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and CVC4.
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ast/simplify: don't bitblast async ROMs declared as `logic`
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Fixes #2020.
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Fix modulo/remainder semantics
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The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
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The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
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Restrict RTLIL::IdString to not contain whitespace or control chars
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This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.
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qbfsat: Add support for CVC4.
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qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
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the default.
Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
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ilang_lexer: fix check for out of range literal
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Commit ca70a104 did not use a correct check.
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verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
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`VERILOG_FRONTEND` namespace.
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Fix small typos in documentation for hierarchy command
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Add `printattrs` command to print attributes of currently selected objects.
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Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
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Co-Authored-By: whitequark <whitequark@whitequark.org>
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Co-Authored-By: whitequark <whitequark@whitequark.org>
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Suppress warning during initial clone of ABC repo
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9dedac50 introduced this harmless but disconcerting warning, which was emitted
when abc/ did not yet exist and was about to be cloned:
/bin/sh: line 0: cd: abc: No such file or directory
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Add extmodule support to firrtl backend
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The current firrtl backend emits blackboxes as standard modules
with an empty body, but this causes the firrtl compiler to
optimize out entire circuits due to the absence of any drivers.
Yosys already tags blackboxes with a (*blackbox*) attribute, so this
commit just propagates this change to firrtl's syntax for blackboxes.
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firrtl: Accept techmapped cell types in FIRRTL backend.
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