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| * | | | | | | | Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `outbit_to_cell`.
| * | | | | | | | Replace `std::map` with `dict` for `TechmapWires` type.Alberto Gonzalez2020-05-141-1/+1
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| * | | | | | | | Replace `std::map` with `dict` for `celltypeMap`.Alberto Gonzalez2020-05-141-3/+3
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| * | | | | | | | Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.Alberto Gonzalez2020-05-141-4/+4
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| * | | | | | | | Replace `std::map` with `dict` for `positional_ports`.Alberto Gonzalez2020-05-141-1/+1
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| * | | | | | | | Add specialized `hash()` for type `dict` and use a `dict` instead of a ↵Alberto Gonzalez2020-05-143-10/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `std::map` for `techmap_cache` and `techmap_do_cache`.
| * | | | | | | | Replace `std::map` with `dict` for `simplemap_mappers`.Alberto Gonzalez2020-05-143-5/+5
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| * | | | | | | | Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-10/+10
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| * | | | | | | | Replace `std::string` and `RTLIL::IdString` with `IdString` in ↵Alberto Gonzalez2020-05-141-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `passes/techmap/techmap.cc`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | | | | | | | Do not modify design modules while iterating over `modules()`.Alberto Gonzalez2020-05-141-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | | | | | | | Clean up pseudo-private member usage, superfluous `std::vector` ↵Alberto Gonzalez2020-05-141-76/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
* | | | | | | | | Merge pull request #2081 from YosysHQ/eddie/blackbox_astEddie Hung2020-05-301-25/+1
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | blackbox: use Module::makeblackbox() method
| * | | | | | | | | blackbox: re-use existing Module::makeblackbox() methodEddie Hung2020-05-251-25/+1
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* | | | | | | | | Merge pull request #2018 from boqwxp/qbfsat-timeoutclairexen2020-05-303-18/+84
|\ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|/ / |/| | | | | | | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
| * | | | | | | | smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.Alberto Gonzalez2020-05-291-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Co-Authored-By: clairexen <claire@symbioticeda.com>
| * | | | | | | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, ↵Alberto Gonzalez2020-05-253-18/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and CVC4.
* | | | | | | | | Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logicclairexen2020-05-293-2/+11
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | ast/simplify: don't bitblast async ROMs declared as `logic`
| * | | | | | | | | ast/simplify: don't bitblast async ROMs declared as `logic`.whitequark2020-05-053-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #2020.
* | | | | | | | | | Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-2926-40/+540
|\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | Fix modulo/remainder semantics
| * | | | | | | | | | Document division and modulo cellsXiretza2020-05-281-0/+23
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| * | | | | | | | | | Update CHANGELOGXiretza2020-05-281-0/+1
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| * | | | | | | | | | Add comments for mod/div semantics to rtlil.hXiretza2020-05-281-0/+4
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| * | | | | | | | | | Expand tests/simple/constmuldivmod.vXiretza2020-05-281-1/+41
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| * | | | | | | | | | Add flooring division operatorXiretza2020-05-2819-24/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
| * | | | | | | | | | Add flooring modulo operatorXiretza2020-05-2823-37/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* | | | | | | | | | | Merge pull request #2092 from whitequark/rtlil-no-space-controlclairexen2020-05-292-6/+11
|\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Restrict RTLIL::IdString to not contain whitespace or control chars
| * | | | | | | | | | | Restrict RTLIL::IdString to not contain whitespace or control chars.whitequark2020-05-292-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an existing invariant (most backends can't cope with these) but one that was not checked or documented.
* | | | | | | | | | | | Merge pull request #2017 from boqwxp/qbfsat-cvc4clairexen2020-05-291-2/+6
|\ \ \ \ \ \ \ \ \ \ \ \ | | |_|_|/ / / / / / / / | |/| | | | | | | | | | qbfsat: Add support for CVC4.
| * | | | | | | | | | | qbfsat: Add support for CVC4.Alberto Gonzalez2020-05-251-2/+6
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* | | | | | | | | | | | Merge pull request #2016 from boqwxp/qbfsat-yicesclairexen2020-05-292-21/+52
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
| * | | | | | | | | | | qbfsat: Move SMT2 info statements back to the top of the file.Alberto Gonzalez2020-05-251-3/+3
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| * | | | | | | | | | | qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices ↵Alberto Gonzalez2020-05-252-23/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the default. Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
* | | | | | | | | | | | Merge pull request #2097 from whitequark/ilang_lexer-fix-erangewhitequark2020-05-291-1/+3
|\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | ilang_lexer: fix check for out of range literal
| * | | | | | | | | | | | ilang_lexer: fix check for out of range literal.whitequark2020-05-291-1/+3
| | |_|/ / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ca70a104 did not use a correct check.
* | | | | | | | | | | | Merge pull request #2033 from boqwxp/cleanup-verilog-lexerwhitequark2020-05-291-6/+5
|\ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / |/| | | | | | | | | | | verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
| * | | | | | | | | | | verilog: Move lexer location variables from global namespace to ↵Alberto Gonzalez2020-05-061-6/+5
| | |_|_|_|/ / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `VERILOG_FRONTEND` namespace.
* | | | | | | | | | | Merge pull request #2095 from rswarbrick/hier-typowhitequark2020-05-281-2/+2
|\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Fix small typos in documentation for hierarchy command
| * | | | | | | | | | | Fix small typos in documentation for hierarchy commandRupert Swarbrick2020-05-281-2/+2
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* | | | | | | | | | | | Merge pull request #2091 from boqwxp/printattrswhitequark2020-05-283-0/+105
|\ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / |/| | | | | | | | | | | Add `printattrs` command to print attributes of currently selected objects.
| * | | | | | | | | | | printattrs: Simplify `get_indent_str()`.Alberto Gonzalez2020-05-281-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
| * | | | | | | | | | | printattrs: Refactor indentation string building for clarity.Alberto Gonzalez2020-05-271-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Co-Authored-By: whitequark <whitequark@whitequark.org>
| * | | | | | | | | | | printattrs: Add test.Alberto Gonzalez2020-05-271-0/+14
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| * | | | | | | | | | | printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.Alberto Gonzalez2020-05-271-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Co-Authored-By: whitequark <whitequark@whitequark.org>
| * | | | | | | | | | | misc: Add `printattrs` command.Alberto Gonzalez2020-05-272-0/+80
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* | | | | | | | | | | Merge pull request #2051 from Xiretza/makefile-cd-warningwhitequark2020-05-281-1/+1
|\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Suppress warning during initial clone of ABC repo
| * | | | | | | | | | | Suppress warning during initial clone of ABC repoXiretza2020-05-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 9dedac50 introduced this harmless but disconcerting warning, which was emitted when abc/ did not yet exist and was about to be cloned: /bin/sh: line 0: cd: abc: No such file or directory
* | | | | | | | | | | | Merge pull request #2031 from epfl-vlsc/masterwhitequark2020-05-281-1/+40
|\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | Add extmodule support to firrtl backend
| * | | | | | | | | | | | Formatting fixesSahand Kashani2020-05-061-14/+7
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| * | | | | | | | | | | | Add extmodule support to firrtl backendSahand Kashani2020-05-061-1/+47
| | |_|/ / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current firrtl backend emits blackboxes as standard modules with an empty body, but this causes the firrtl compiler to optimize out entire circuits due to the absence of any drivers. Yosys already tags blackboxes with a (*blackbox*) attribute, so this commit just propagates this change to firrtl's syntax for blackboxes.
* | | | | | | | | | | | Merge pull request #2063 from boqwxp/techmapped-firrtlwhitequark2020-05-281-10/+12
|\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | firrtl: Accept techmapped cell types in FIRRTL backend.
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