Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Merge pull request #891 from YosysHQ/xilinx_keep | David Shah | 2019-03-22 | 2 | -25/+31 | |
| |\ \ | | |/ | |/| | xilinx: Add keep attribute where appropriate | |||||
| | * | xilinx: Add keep attribute where appropriate | David Shah | 2019-03-22 | 2 | -25/+31 | |
| |/ | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | Improve "read_verilog -dump_vlog[12]" handling of upto ranges | Clifford Wolf | 2019-03-21 | 1 | -3/+6 | |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Improve read_verilog debug output capabilities | Clifford Wolf | 2019-03-21 | 3 | -15/+42 | |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
* | | Add '-nosrl' option to synth_xilinx | Eddie Hung | 2019-03-21 | 1 | -6/+16 | |
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* | | Opt | Eddie Hung | 2019-03-21 | 1 | -1/+1 | |
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* | | Fix spacing | Eddie Hung | 2019-03-20 | 1 | -239/+239 | |
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* | | Fine tune cells_map.v | Eddie Hung | 2019-03-20 | 1 | -19/+15 | |
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* | | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length | Eddie Hung | 2019-03-19 | 2 | -58/+34 | |
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* | | Add support for variable length Xilinx SRL > 128 | Eddie Hung | 2019-03-19 | 2 | -17/+67 | |
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* | | Restore original synth_xilinx commands | Eddie Hung | 2019-03-19 | 1 | -1/+2 | |
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* | | Fix spacing | Eddie Hung | 2019-03-19 | 1 | -1/+1 | |
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* | | shregmap -tech xilinx to delete $shiftx for var length SRL | Eddie Hung | 2019-03-19 | 1 | -10/+3 | |
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* | | Fix INIT for variable length SRs that have been bumped up one | Eddie Hung | 2019-03-19 | 1 | -1/+1 | |
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* | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-19 | 53 | -38/+2398 | |
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| * | Merge pull request #885 from YosysHQ/clifford/fix873 | Clifford Wolf | 2019-03-19 | 1 | -2/+4 | |
| |\ | | | | | | | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 | |||||
| | * | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 | Clifford Wolf | 2019-03-19 | 1 | -2/+4 | |
| |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge pull request #808 from eddiehung/read_aiger | Eddie Hung | 2019-03-19 | 35 | -6/+632 | |
| |\ | | | | | | | Add new read_aiger frontend | |||||
| | * | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-03-19 | 113 | -792/+6364 | |
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| * | | Merge pull request #884 from zachjs/master | Clifford Wolf | 2019-03-19 | 2 | -1/+61 | |
| |\ \ | | | | | | | | | fix local name resolution in prefix constructs | |||||
| | * | | fix local name resolution in prefix constructs | Zachary Snow | 2019-03-18 | 2 | -1/+61 | |
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| * | | Update issue template | Clifford Wolf | 2019-03-17 | 1 | -5/+5 | |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Update issue template | Clifford Wolf | 2019-03-17 | 1 | -0/+8 | |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #877 from FelixVi/master | Clifford Wolf | 2019-03-16 | 1 | -1/+4 | |
| |\ \ | | | | | | | | | Add note about test requirements in README | |||||
| | * | | Add note about test requirements in README | Felix Vietmeyer | 2019-03-16 | 1 | -1/+4 | |
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| * | | Improve mix of src/wire/wirebit coverage in "mutate -list" | Clifford Wolf | 2019-03-16 | 1 | -29/+84 | |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #876 from YosysHQ/clifford/fmcombine | Clifford Wolf | 2019-03-16 | 4 | -17/+374 | |
| |\ \ | | | | | | | | | Add fmcombine pass | |||||
| | * | | Add "fmcombine -fwd -bwd -nop" | Clifford Wolf | 2019-03-15 | 1 | -10/+59 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add fmcombine pass | Clifford Wolf | 2019-03-15 | 4 | -17/+325 | |
| |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #875 from YosysHQ/clifford/mutate | Clifford Wolf | 2019-03-15 | 4 | -5/+862 | |
| |\ \ | | | | | | | | | Add "mutate" pass | |||||
| | * | | Improvements in "mutate" list-reduce algorithm | Clifford Wolf | 2019-03-15 | 1 | -13/+36 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add "mutate -cfg", improve pick_cover behavior | Clifford Wolf | 2019-03-14 | 1 | -46/+101 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add a strictly coverage-driven mutation selection strategy | Clifford Wolf | 2019-03-14 | 1 | -1/+70 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Improve "mutate" wire coverage metric | Clifford Wolf | 2019-03-14 | 1 | -1/+16 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add more mutation types, improve mutation src cover | Clifford Wolf | 2019-03-14 | 1 | -92/+268 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Fix smtbmc.py handling of zero appended steps | Clifford Wolf | 2019-03-14 | 1 | -5/+5 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add "mutate" command DB reduce functionality | Clifford Wolf | 2019-03-14 | 1 | -12/+181 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add hashlib "<container>::element(int n)" methods | Clifford Wolf | 2019-03-14 | 1 | -0/+6 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add "mutate -mode inv", various other mutate improvements | Clifford Wolf | 2019-03-14 | 1 | -99/+213 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add basic "mutate -list N" framework | Clifford Wolf | 2019-03-14 | 2 | -0/+230 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Disable realmath tests | Clifford Wolf | 2019-03-15 | 1 | -1/+1 | |
| |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #874 from YosysHQ/clifford/andopt | Clifford Wolf | 2019-03-14 | 1 | -0/+7 | |
| |\ \ | | | | | | | | | Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327 | |||||
| | * | | Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327 | Clifford Wolf | 2019-03-14 | 1 | -0/+7 | |
| |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #872 from YosysHQ/clifford/pmuxfix | Clifford Wolf | 2019-03-14 | 2 | -1/+10 | |
| |\ \ | | | | | | | | | Improve handling of "full_case" attributes | |||||
| | * | | Improve handling of "full_case" attributes | Clifford Wolf | 2019-03-14 | 1 | -0/+9 | |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Fix a syntax bug in ilang backend related to process case statements | Clifford Wolf | 2019-03-14 | 1 | -1/+1 | |
| |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #869 from cr1901/win-shell | Clifford Wolf | 2019-03-14 | 3 | -1/+377 | |
| |\ \ | | | | | | | | | Install launcher executable when running yosys-smtbmc on Windows. | |||||
| | * | | Install launcher executable when running yosys-smtbmc on Windows. | William D. Jones | 2019-03-13 | 3 | -1/+377 | |
| | | | | | | | | | | | | | | | | Signed-off-by: William D. Jones <thor0505@comcast.net> | |||||
| | | * | Add author name | Eddie Hung | 2019-03-19 | 1 | -0/+1 | |
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| | | * | Add aiger tests to make tests | Eddie Hung | 2019-02-19 | 1 | -0/+1 | |
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