Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Working ABC9 script | Eddie Hung | 2019-04-17 | 1 | -2/+2 |
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* | Stop topological sort at abc_flop_q | Eddie Hung | 2019-04-17 | 1 | -7/+13 |
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* | Mark seq output ports with "abc_flop_q" attr | Eddie Hung | 2019-04-17 | 1 | -24/+24 |
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* | Also update Makefile.inc | Eddie Hung | 2019-04-17 | 1 | -3/+3 |
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* | synth_ice40 to use renamed files | Eddie Hung | 2019-04-17 | 1 | -2/+2 |
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* | Rename to abc.* | Eddie Hung | 2019-04-17 | 3 | -0/+0 |
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* | Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" | Eddie Hung | 2019-04-17 | 7 | -102/+35 |
| | | | | This reverts commit a7632ab3326c5247b8152a53808413b259c13253. | ||||
* | Try using an ICE40_CARRY_LUT primitive to avoid ABC issues | Eddie Hung | 2019-04-17 | 7 | -35/+102 |
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* | Remove init* from xaiger, also topo-sort cells for box flow | Eddie Hung | 2019-04-17 | 1 | -95/+157 |
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* | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-17 | 1 | -1/+1 |
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| * | Update to ABC d1b6413 | Clifford Wolf | 2019-04-17 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Ignore a/i/o/h XAIGER extensions | Eddie Hung | 2019-04-17 | 1 | -0/+7 |
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* | | Fix spacing | Eddie Hung | 2019-04-17 | 1 | -5/+5 |
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* | | Optimise | Eddie Hung | 2019-04-16 | 1 | -4/+3 |
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* | | Add SB_LUT4 to box library | Eddie Hung | 2019-04-16 | 3 | -0/+16 |
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* | | Add ice40 box files | Eddie Hung | 2019-04-16 | 6 | -1/+27 |
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* | | abc9 to output some more info | Eddie Hung | 2019-04-16 | 1 | -1/+2 |
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* | | CIs before PIs; also sort each cell's connections before iterating | Eddie Hung | 2019-04-16 | 1 | -5/+7 |
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* | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-16 | 1 | -28/+0 |
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| * | Merge pull request #939 from YosysHQ/revert895 | Eddie Hung | 2019-04-16 | 1 | -28/+0 |
| |\ | | | | | | | Revert #895 (mux-to-shiftx optimisation) | ||||
| | * | Revert #895 | Eddie Hung | 2019-04-16 | 1 | -28/+0 |
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* | | Port from xc7mux branch | Eddie Hung | 2019-04-16 | 3 | -54/+167 |
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* | | Re-enable partsel.v test | Eddie Hung | 2019-04-16 | 1 | -1/+0 |
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* | | abc9 to call "setundef -zero" behaving as for abc | Eddie Hung | 2019-04-16 | 1 | -0/+3 |
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* | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-15 | 3 | -6/+5 |
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| * | Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch | Eddie Hung | 2019-04-15 | 2 | -4/+3 |
| |\ | | | | | | | Revert "Recognise default entry in case even if all cases covered (fix for #931)" | ||||
| | * | Revert "Recognise default entry in case even if all cases covered (fix for ↵ | Eddie Hung | 2019-04-15 | 2 | -4/+3 |
| |/ | | | | | | | #931)" | ||||
| * | Merge pull request #936 from YosysHQ/README-fix-quotes | Eddie Hung | 2019-04-15 | 1 | -2/+2 |
| |\ | | | | | | | README: fix some incorrect quoting | ||||
| | * | README: fix some incorrect quoting. | whitequark | 2019-04-15 | 1 | -2/+2 |
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* | | Forgot backslashes | Eddie Hung | 2019-04-12 | 1 | -1/+1 |
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* | | Handle __dummy_o__ and __const[01]__ in read_aiger not abc | Eddie Hung | 2019-04-12 | 2 | -18/+8 |
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* | | abc to ignore __dummy_o__ and __const[01]__ when re-integrating | Eddie Hung | 2019-04-12 | 1 | -6/+20 |
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* | | Output __const0__ and __const1__ CIs | Eddie Hung | 2019-04-12 | 1 | -7/+10 |
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* | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-04-12 | 1 | -12/+32 |
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| * | | Fix inout handling for -map option | Eddie Hung | 2019-04-12 | 1 | -10/+30 |
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* | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-04-12 | 0 | -0/+0 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-12 | 7 | -50/+76 |
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* | | | Use -map instead of -symbols for aiger | Eddie Hung | 2019-04-12 | 1 | -2/+3 |
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* | | | ci_bits and co_bits now a list, order is important for ABC | Eddie Hung | 2019-04-12 | 1 | -24/+34 |
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* | | | Also cope with duplicated CIs | Eddie Hung | 2019-04-12 | 1 | -5/+23 |
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* | | | WIP | Eddie Hung | 2019-04-12 | 1 | -14/+68 |
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* | | | Comment out | Eddie Hung | 2019-04-12 | 1 | -1/+1 |
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* | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-12 | 2 | -1/+14 |
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* | | | Cope with an output having same name as an input (i.e. CO) | Eddie Hung | 2019-04-12 | 1 | -5/+23 |
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* | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-12 | 7 | -50/+76 |
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| * | Merge pull request #928 from litghost/add_xc7_sim_models | Eddie Hung | 2019-04-12 | 3 | -41/+60 |
| |\ | | | | | | | Add additional cells sim models for core 7-series primitives. | ||||
| | * | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 3 | -52/+14 |
| | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | * | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 |
| | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | * | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 |
| | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | | Merge pull request #933 from dh73/master | Clifford Wolf | 2019-04-12 | 1 | -3/+9 |
| |\ \ | | | | | | | | | Fixing issues in CycloneV cell sim |