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* Working ABC9 scriptEddie Hung2019-04-171-2/+2
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* Stop topological sort at abc_flop_qEddie Hung2019-04-171-7/+13
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* Mark seq output ports with "abc_flop_q" attrEddie Hung2019-04-171-24/+24
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* Also update Makefile.incEddie Hung2019-04-171-3/+3
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* synth_ice40 to use renamed filesEddie Hung2019-04-171-2/+2
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* Rename to abc.*Eddie Hung2019-04-173-0/+0
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* Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"Eddie Hung2019-04-177-102/+35
| | | | This reverts commit a7632ab3326c5247b8152a53808413b259c13253.
* Try using an ICE40_CARRY_LUT primitive to avoid ABC issuesEddie Hung2019-04-177-35/+102
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* Remove init* from xaiger, also topo-sort cells for box flowEddie Hung2019-04-171-95/+157
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* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-171-1/+1
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| * Update to ABC d1b6413Clifford Wolf2019-04-171-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Ignore a/i/o/h XAIGER extensionsEddie Hung2019-04-171-0/+7
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* | Fix spacingEddie Hung2019-04-171-5/+5
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* | OptimiseEddie Hung2019-04-161-4/+3
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* | Add SB_LUT4 to box libraryEddie Hung2019-04-163-0/+16
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* | Add ice40 box filesEddie Hung2019-04-166-1/+27
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* | abc9 to output some more infoEddie Hung2019-04-161-1/+2
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* | CIs before PIs; also sort each cell's connections before iteratingEddie Hung2019-04-161-5/+7
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-161-28/+0
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| * Merge pull request #939 from YosysHQ/revert895Eddie Hung2019-04-161-28/+0
| |\ | | | | | | Revert #895 (mux-to-shiftx optimisation)
| | * Revert #895Eddie Hung2019-04-161-28/+0
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* | Port from xc7mux branchEddie Hung2019-04-163-54/+167
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* | Re-enable partsel.v testEddie Hung2019-04-161-1/+0
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* | abc9 to call "setundef -zero" behaving as for abcEddie Hung2019-04-161-0/+3
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-153-6/+5
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| * Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatchEddie Hung2019-04-152-4/+3
| |\ | | | | | | Revert "Recognise default entry in case even if all cases covered (fix for #931)"
| | * Revert "Recognise default entry in case even if all cases covered (fix for ↵Eddie Hung2019-04-152-4/+3
| |/ | | | | | | #931)"
| * Merge pull request #936 from YosysHQ/README-fix-quotesEddie Hung2019-04-151-2/+2
| |\ | | | | | | README: fix some incorrect quoting
| | * README: fix some incorrect quoting.whitequark2019-04-151-2/+2
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* | Forgot backslashesEddie Hung2019-04-121-1/+1
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* | Handle __dummy_o__ and __const[01]__ in read_aiger not abcEddie Hung2019-04-122-18/+8
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* | abc to ignore __dummy_o__ and __const[01]__ when re-integratingEddie Hung2019-04-121-6/+20
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* | Output __const0__ and __const1__ CIsEddie Hung2019-04-121-7/+10
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* | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-121-12/+32
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| * | Fix inout handling for -map optionEddie Hung2019-04-121-10/+30
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* | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-120-0/+0
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| * | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-127-50/+76
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* | | Use -map instead of -symbols for aigerEddie Hung2019-04-121-2/+3
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* | | ci_bits and co_bits now a list, order is important for ABCEddie Hung2019-04-121-24/+34
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* | | Also cope with duplicated CIsEddie Hung2019-04-121-5/+23
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* | | WIPEddie Hung2019-04-121-14/+68
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* | | Comment outEddie Hung2019-04-121-1/+1
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* | | Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-122-1/+14
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* | | Cope with an output having same name as an input (i.e. CO)Eddie Hung2019-04-121-5/+23
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* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-127-50/+76
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| * Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
| |\ | | | | | | Add additional cells sim models for core 7-series primitives.
| | * Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Merge pull request #933 from dh73/masterClifford Wolf2019-04-121-3/+9
| |\ \ | | | | | | | | Fixing issues in CycloneV cell sim