aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
* | Removed old SigMap implementationClifford Wolf2015-10-271-224/+0
* | Added hashlib::mfp and new SigMapClifford Wolf2015-10-273-0/+185
* | Improvements in equiv_structClifford Wolf2015-10-251-17/+62
* | Major refactoring of equiv_structClifford Wolf2015-10-252-93/+170
* | Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-2539-161/+168
* | Added "equiv_add -cell"Clifford Wolf2015-10-252-34/+95
* | equiv_struct now creates equiv_merged attributesClifford Wolf2015-10-251-0/+3
* | Improvements in equiv_structClifford Wolf2015-10-241-1/+22
* | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-248-34/+34
* | improvement in "stat"Clifford Wolf2015-10-241-1/+1
* | Fixed driver conflict handling (various cmds)Clifford Wolf2015-10-241-3/+12
* | equiv_purge bugfix, using SigChunk in Yosys namespaceClifford Wolf2015-10-245-5/+8
* | Fixed handling of driver-driver conflicts in wreduceClifford Wolf2015-10-243-9/+42
* | Added equiv_mark commandClifford Wolf2015-10-233-1/+265
* | Disabled "Skipping blackbox module" msg in show commandClifford Wolf2015-10-231-1/+1
* | Added support for ":" as comment symbol after ;-parsingClifford Wolf2015-10-231-1/+1
* | Also merge $equiv cells in equiv_structClifford Wolf2015-10-231-0/+1
* | Improvements in equiv_structClifford Wolf2015-10-231-11/+18
* | Added equiv_purgeClifford Wolf2015-10-222-0/+210
* | Added equiv_struct commandClifford Wolf2015-10-212-0/+188
* | Improved inout handling in equiv_makeClifford Wolf2015-10-211-1/+1
* | Progress on cell help messagesClifford Wolf2015-10-201-18/+114
* | Progress on cell help messagesClifford Wolf2015-10-173-54/+107
* | Progress in yosys-smtbmcClifford Wolf2015-10-151-4/+10
* | Fixed bug in verilog parserClifford Wolf2015-10-151-1/+1
* | Improvements in yosys-smtbmcClifford Wolf2015-10-153-2/+9
* | Bugfixes in handling of "keep" attribute on wiresClifford Wolf2015-10-152-2/+8
* | More "yosys-smtbmc -c" fixesClifford Wolf2015-10-142-9/+30
* | Fixed yosys-smtbmc -cClifford Wolf2015-10-141-2/+2
* | Added "prep" commandClifford Wolf2015-10-142-0/+157
* | Added more cell descriptionsClifford Wolf2015-10-141-0/+85
* | Added first help messages for cell typesClifford Wolf2015-10-146-6/+336
* | Added yosys-smtbmc copyrightClifford Wolf2015-10-143-1/+36
* | Improvements in yosys-smtbmcClifford Wolf2015-10-143-21/+38
* | Added yosys-smtbmcClifford Wolf2015-10-142-1/+20
* | Implemented smtbmc.py -iClifford Wolf2015-10-141-25/+60
* | Added smtbmc.pyClifford Wolf2015-10-134-0/+409
* | Added write_smt2 -wiresClifford Wolf2015-10-131-7/+15
* | Added examples/ top-level directoryClifford Wolf2015-10-1317-4/+7
* | SystemVerilog also has assume(), added implicit -D FORMALClifford Wolf2015-10-133-4/+5
* | Merge branch 'master' of https://github.com/rubund/yosysClifford Wolf2015-10-131-18/+18
|\ \
| * | Use DESTDIR as defined in https://www.gnu.org/prep/standards/html_node/DESTDI...Ruben Undheim2015-10-111-13/+13
| * | Use LDFLAGS, CXXFLAGS and CPPFLAGS from the environment when buildingRuben Undheim2015-10-111-7/+7
* | | Fixed "flatten" for unconnected inout portsClifford Wolf2015-10-131-1/+1
|/ /
* | Added support for "parameter" and "localparam" in global contextClifford Wolf2015-10-071-0/+2
* | Fixed complexity of assigning to vectors in constant functionsClifford Wolf2015-10-011-0/+3
* | Fixed detection of unconditional $readmem[hb]Clifford Wolf2015-09-301-4/+11
* | Added edgetypes commandClifford Wolf2015-09-272-0/+107
* | Some cleanups in qwpClifford Wolf2015-09-261-7/+16
* | Added "test_cell -noeval"Clifford Wolf2015-09-251-1/+10
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 21:31:56 +0000