iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	ECP5: implement all Diamond I/O buffer primitives.	whitequark	2019-06-06	1	-0/+15
*	Merge pull request #1004 from YosysHQ/clifford/fix1002	Clifford Wolf	2019-05-12	1	-3/+11
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\| *	Fix handling of glob_abort_cnt in opt_muxtree, fixes #1002	Clifford Wolf	2019-05-12	1	-3/+11
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*	Merge pull request #1003 from makaimann/zinit-all	Clifford Wolf	2019-05-11	1	-1/+1
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\| *	Zinit option '-singleton' -> '-all'	Makai Mann	2019-05-10	1	-1/+1
* \|	Add "fmcombine -initeq -anyeq"	Clifford Wolf	2019-05-11	1	-3/+38
* \|	Add "stat -tech xilinx"	Clifford Wolf	2019-05-11	2	-4/+74
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*	Merge pull request #1000 from bwidawsk/synth-format	Clifford Wolf	2019-05-09	2	-222/+224
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\| *	Fix formatting for synth_intel.cc	Ben Widawsky	2019-05-09	1	-222/+211
\| *	Add a .clang-format	Ben Widawsky	2019-05-09	1	-0/+13
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*	Add $stop to documentation	Clifford Wolf	2019-05-09	1	-3/+4
*	Remove added newline (by re-running minisat 00_UPDATE.sh)	Clifford Wolf	2019-05-08	1	-1/+0
*	Merge pull request #991 from kristofferkoch/gcc9-warnings	Clifford Wolf	2019-05-08	5	-5/+9
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\| *	Fix all warnings that occurred when compiling with gcc9	Kristoffer Ellersgaard Koch	2019-05-08	5	-5/+9
* \|	Merge pull request #998 from mdaiter/get_bool_attribute_opts	Clifford Wolf	2019-05-08	1	-4/+8
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\| * \|	Minor optimization to get_attribute_bool	Matthew Daiter	2019-05-07	1	-4/+8
* \| \|	Add test case from #997	Clifford Wolf	2019-05-07	1	-0/+12
* \| \|	Fix handling of partial init attributes in write_verilog, fixes #997	Clifford Wolf	2019-05-07	1	-1/+2
* \| \|	Merge pull request #996 from mdaiter/ceil_log2_opts	Clifford Wolf	2019-05-07	2	-3/+5
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\| * \| \|	Optimize ceil_log2 function	Matthew Daiter	2019-05-07	2	-3/+5
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* \| \|	Add "synth_xilinx -arch"	Clifford Wolf	2019-05-07	1	-1/+13
* \| \|	More opt_clean cleanups	Clifford Wolf	2019-05-07	1	-26/+36
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* \|	Merge pull request #946 from YosysHQ/clifford/specify	Clifford Wolf	2019-05-06	19	-51/+810
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\| * \|	Improve tests/various/specify.ys	Clifford Wolf	2019-05-06	1	-2/+32
\| * \|	Add "real" keyword to ilang format	Clifford Wolf	2019-05-06	3	-2/+12
\| * \|	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify	Clifford Wolf	2019-05-06	3	-12/+32
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\| * \| \|	Improve write_verilog specify support	Clifford Wolf	2019-05-04	3	-16/+75
\| * \| \|	Update README	Clifford Wolf	2019-05-04	1	-5/+1
\| * \| \|	More testing	Eddie Hung	2019-05-03	2	-2/+5
\| * \| \|	Fix spacing	Eddie Hung	2019-05-03	1	-6/+6
\| * \| \|	Add quick-and-dirty specify tests	Eddie Hung	2019-05-03	2	-0/+53
\| * \| \|	Merge remote-tracking branch 'origin/master' into clifford/specify	Eddie Hung	2019-05-03	40	-405/+931
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\| * \| \| \|	Add specify support to README	Clifford Wolf	2019-04-23	1	-0/+5
\| * \| \| \|	Improve $specrule interface	Clifford Wolf	2019-04-23	4	-13/+23
\| * \| \| \|	Improve $specrule interface	Clifford Wolf	2019-04-23	3	-24/+24
\| * \| \| \|	Add $specrule cells for $setup/$hold/$skew specify rules	Clifford Wolf	2019-04-23	9	-6/+133
\| * \| \| \|	Preserve $specify[23] cells	Clifford Wolf	2019-04-23	1	-1/+1
\| * \| \| \|	Allow $specify[23] cells in blackbox modules	Clifford Wolf	2019-04-23	1	-0/+6
\| * \| \| \|	Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...	Clifford Wolf	2019-04-23	4	-76/+76
\| * \| \| \|	Add $specify2/$specify3 support to write_verilog	Clifford Wolf	2019-04-23	1	-0/+47
\| * \| \| \|	Add support for $assert/$assume/$cover to write_verilog	Clifford Wolf	2019-04-23	1	-0/+10
\| * \| \| \|	Add CellTypes support for $specify2 and $specify3	Clifford Wolf	2019-04-23	2	-0/+7
\| * \| \| \|	Add InternalCellChecker support for $specify2 and $specify3	Clifford Wolf	2019-04-23	1	-7/+21
\| * \| \| \|	Checking and fixing specify cells in genRTLIL	Clifford Wolf	2019-04-23	1	-1/+15
\| * \| \| \|	Un-break default specify parser	Clifford Wolf	2019-04-23	1	-0/+1
\| * \| \| \|	Add specify parser	Clifford Wolf	2019-04-23	5	-33/+253
\| * \| \| \|	Add $specify2 and $specify3 cells to simlib	Clifford Wolf	2019-04-23	1	-0/+147
* \| \| \| \|	Merge pull request #975 from YosysHQ/clifford/fix968	Clifford Wolf	2019-05-06	3	-13/+66
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\| * \ \ \ \	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968	Clifford Wolf	2019-05-06	35	-290/+787
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\| * \| \| \| \| \|	Further improve unused-detection for opt_clean driver-driver conflict warning	Clifford Wolf	2019-05-03	1	-5/+8