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* Merge pull request #1609 from YosysHQ/clifford/fix1596Clifford Wolf2020-01-021-4/+25
|\ | | | | Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
| * Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputsClifford Wolf2020-01-021-4/+25
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-0213-48/+52
|\ \ | | | | | | "abc -dff" to no longer retime by default
| * | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-3011-12/+12
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| * | Disable synth_gowin -abc9 as it offers no advantages yetEddie Hung2019-12-301-12/+12
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| * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-3011-13/+13
| | | | | | | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
| * | Revert "ABC to call retime all the time"Eddie Hung2019-12-301-11/+15
| | | | | | | | | | | | This reverts commit 9aa94370a54c016421740d2ce32ef0aa338d0dbd.
* | | Merge pull request #1608 from YosysHQ/eddie/ifndef_YOSYSEddie Hung2020-01-021-6/+6
|\ \ \ | |_|/ |/| | ifdef __ICARUS__ -> ifndef YOSYS
| * | ifdef __ICARUS__ -> ifndef YOSYSEddie Hung2020-01-011-6/+6
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* | Merge pull request #1606 from YosysHQ/eddie/improve_testsEddie Hung2020-01-0110-19/+20
|\ \ | | | | | | Fix a few issues in tests/arch/*
| * | Revert insertion of 'reg', leave note behindEddie Hung2020-01-011-1/+2
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| * | Fix anlogic async flop mappingEddie Hung2020-01-011-8/+8
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| * | Do not do call equiv_opt when no sim model existsEddie Hung2019-12-312-4/+4
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| * | Fix warningsEddie Hung2019-12-312-2/+2
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| * | Call equiv_opt with -multiclock and -assertEddie Hung2019-12-315-5/+5
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* | | Merge pull request #1605 from YosysHQ/iopad_fixMiodrag Milanović2020-01-012-0/+22
|\ \ \ | |/ / |/| | iopad mapping should take care of existing io buffers
| * | Added a test caseMiodrag Milanovic2020-01-011-0/+19
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| * | take skip wire bits into accountMiodrag Milanovic2020-01-011-0/+3
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* | GrammarEddie Hung2019-12-301-1/+1
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* | Update timings for Xilinx S7 cellsEddie Hung2019-12-301-15/+35
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* | Merge pull request #1589 from YosysHQ/iopad_defaultMiodrag Milanović2019-12-3020-71/+67
|\ \ | |/ |/| Make iopad option default for all xilinx flows
| * Fix new testsMiodrag Milanovic2019-12-283-6/+6
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| * Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-2820-150/+1614
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| * | Make test without iopadsMiodrag Milanovic2019-12-2817-51/+51
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| * | Revert "Fix xilinx tests, when iopads are default"Miodrag Milanovic2019-12-2816-40/+40
| | | | | | | | | | | | This reverts commit 477e43d921d204c6bc6403109fea6506802c948c.
| * | Addressed review commentsMiodrag Milanovic2019-12-212-3/+3
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| * | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
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| * | Fix xilinx tests, when iopads are defaultMiodrag Milanovic2019-12-2117-42/+44
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| * | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
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* | | Merge pull request #1599 from YosysHQ/eddie/retry_1588Eddie Hung2019-12-304-20/+87
|\ \ \ | | | | | | | | Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
| * | | Add #1598 testcaseEddie Hung2019-12-273-0/+48
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| * | | write_xaiger: inherit port ordering from original moduleEddie Hung2019-12-271-5/+16
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| * | | Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"Eddie Hung2019-12-271-19/+27
| | |/ | |/| | | | | | | | | | This reverts commit 92654f73ea92ee9e390c8ab50d8cb51c47a7ffa9, reversing changes made to 3e14ff16676884a1f65cf0eeb0ca9cb1958b8804.
* | | Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5Eddie Hung2019-12-303-14/+6
|\ \ \ | |/ / |/| | Nitpick cleanup for ecp5
| * | Update resource countEddie Hung2019-12-281-3/+3
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| * | Nitpick cleanup for ecp5Eddie Hung2019-12-272-11/+3
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* | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-12-271-27/+19
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| * \ Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanupDavid Shah2019-12-271-27/+19
| |\ \ | | | | | | | | Revert "write_xaiger: only instantiate each whitebox cell type once"
| | * | Revert "write_xaiger: only instantiate each whitebox cell type once"David Shah2019-12-271-27/+19
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* / / write_xaiger: simplify c{i,o}_bitsEddie Hung2019-12-271-12/+6
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* | fixed invalid charMiodrag Milanovic2019-12-251-1/+1
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* | iopadmap: Emit tristate buffers with const OE for some edge cases.Marcin Kościelnicki2019-12-252-23/+91
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* | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgenMarcin Kościelnicki2019-12-2512-81/+1136
|\ \ | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support.
| * | Minor nit fixesMarcin Kościelnicki2019-12-251-2/+2
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| * | Add DSP cascade testsEddie Hung2019-12-231-0/+89
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| * | Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG tooEddie Hung2019-12-231-8/+18
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| * | Fix CEA/CEB checkEddie Hung2019-12-231-2/+2
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| * | Fix checking CE[AB] and for direct connectionsEddie Hung2019-12-231-18/+40
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| * | Support unregistered cascades for A and B inputsEddie Hung2019-12-231-47/+74
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| * | Add DSP48A* PCOUT -> PCIN cascade supportEddie Hung2019-12-231-10/+10
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