iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Add support for cell arrays	Clifford Wolf	2014-06-07	6	-1/+70
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*	Added support for repeat stmt in const functions	Clifford Wolf	2014-06-07	1	-0/+19
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*	further improved const function support	Clifford Wolf	2014-06-07	3	-17/+22
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*	made the generate..endgenrate keywords optional	Clifford Wolf	2014-06-06	1	-4/+8
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*	improved const function support	Clifford Wolf	2014-06-06	3	-5/+41
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*	fix functions with no block (but single statement, loop, etc.)	Clifford Wolf	2014-06-06	1	-11/+4
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*	Added tests/simple/repwhile.v	Clifford Wolf	2014-06-06	1	-0/+20
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*	improved ast simplify of const functions	Clifford Wolf	2014-06-06	1	-7/+28
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*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06	4	-1/+31
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*	Improved error message for options after front-end filename arguments	Clifford Wolf	2014-06-04	2	-1/+5
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*	added tee cmd	Clifford Wolf	2014-06-03	2	-0/+89
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*	Fixed log messages in memory_dff	Clifford Wolf	2014-06-01	1	-0/+2
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*	Updated ABC to rev fa4404b395f0	Clifford Wolf	2014-05-29	1	-1/+1
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*	Merge pull request #36 from hansiglaser/master	Clifford Wolf	2014-05-29	4	-8/+54
\|\ \| \| \| \|	Various changes merged
\| *	added log_header to miter and expose pass, show cell type for exposed ports	Johann Glaser	2014-05-28	2	-3/+9
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\| *	new flags -ignore_miss_func and -ignore_miss_dir for read_liberty	Johann Glaser	2014-05-28	1	-4/+40
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\| *	be more verbose when techmap yielded processes	Johann Glaser	2014-05-26	1	-1/+5
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*	Fixed bug in opt_reduce (see vloghammer issue_044)	Clifford Wolf	2014-05-12	1	-1/+4
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*	fixed syntax error in dot file created by "show" command	Clifford Wolf	2014-05-10	1	-1/+1
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-05-09	5	-114/+87
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\| *	Progress in presentation	Clifford Wolf	2014-05-06	1	-8/+63
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\| *	Improved ezsat stand-alone tests	Clifford Wolf	2014-05-06	4	-106/+24
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* \|	Updated ABC to 67c84cdd49e4	Clifford Wolf	2014-05-09	1	-1/+1
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*	workaround for OpenBSD 'stdout' implementation	Clifford Wolf	2014-05-03	1	-1/+2
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*	workaround for OpenBSD 'stdin' implementation	Clifford Wolf	2014-05-02	1	-1/+2
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*	Merge pull request #35 from bentley/dox	Clifford Wolf	2014-05-02	2	-32/+32
\|\ \| \| \| \|	Typos and grammar fixes through chapter 4.
\| *	Typos and grammar fixes through chapter 4.	Anthony J. Bentley	2014-05-02	2	-32/+32
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*	Fixed clang -Wdeprecated-register warnings	Clifford Wolf	2014-04-20	2	-0/+12
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*	Replaced depricated %name-prefix= bison directive	Clifford Wolf	2014-04-20	2	-2/+2
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*	minisat compile fix	Clifford Wolf	2014-04-20	3	-2/+25
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*	Updated README	Clifford Wolf	2014-04-18	1	-18/+11
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*	Merge pull request #33 from bentley/dox	Clifford Wolf	2014-04-11	3	-21/+21
\|\ \| \| \| \|	Typos and grammar fixes through chapter 2.
\| *	Typos and grammar fixes through chapter 2.	Anthony J. Bentley	2014-04-11	3	-21/+21
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*	Merge pull request #31 from bentley/posix-rm	Clifford Wolf	2014-04-05	3	-6/+6
\|\ \| \| \| \|	Remove non-POSIX 'rm -v'.
\| *	POSIX find requires a path argument.	Anthony J. Bentley	2014-04-04	2	-2/+2
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\| *	Remove non-POSIX 'rm -v'.	Anthony J. Bentley	2014-04-04	1	-4/+4
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*	Added SIMLIB_NOLUT to simlib.v	Clifford Wolf	2014-04-02	1	-0/+2
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*	Added SIMLIB_NOSR to simlib.v	Clifford Wolf	2014-04-02	1	-0/+6
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*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31	5	-1/+207
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*	Fixed mapping of Verific WIDE_DFFRS operator	Clifford Wolf	2014-03-20	1	-2/+2
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*	Fixed mapping of Verific FADD primitive with unconnected outputs	Clifford Wolf	2014-03-20	1	-4/+5
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*	Fixed performance problem in opt_mux with nets driven by many conflicting ↵	Clifford Wolf	2014-03-19	1	-1/+6
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*	Progress in Verific bindings	Clifford Wolf	2014-03-17	1	-8/+51
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*	Fixed typo in RTLIL::Module::addAdff()	Clifford Wolf	2014-03-17	1	-1/+1
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*	Progress in Verific bindings	Clifford Wolf	2014-03-17	1	-5/+50
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*	Progress in Verific bindings	Clifford Wolf	2014-03-17	4	-2/+15
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*	Added support for memories to verific bindings	Clifford Wolf	2014-03-16	2	-1/+86
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*	Use Verific Net::{IsGnd,IsPwr} API in Verific bindings	Clifford Wolf	2014-03-16	1	-27/+11
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*	Fixed typo in RTLIL::Module::{addSshl,addSshr}	Clifford Wolf	2014-03-15	1	-2/+2
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*	Progress in Verific bindings	Clifford Wolf	2014-03-15	1	-39/+16
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