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* Added $_BUF_ cell typeClifford Wolf2014-10-035-5/+19
* remove buffers in opt_cleanClifford Wolf2014-10-031-0/+13
* resource sharing of $alu cellsClifford Wolf2014-10-031-3/+21
* set "keep" on modules with $assert cells in "hierarchy"Clifford Wolf2014-09-301-0/+30
* Added support for "keep" on modulesClifford Wolf2014-09-294-2/+9
* namespace YosysClifford Wolf2014-09-2796-557/+850
* Merge pull request #39 from ahmedirfan1983/masterClifford Wolf2014-09-222-9/+62
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| * Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-09-22513-12050/+34829
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* | Re-enabled assert for new logic loops in "share" passClifford Wolf2014-09-211-4/+1
* | Various improvements regarding logic loops in "share" resultsClifford Wolf2014-09-211-37/+108
* | Logic loop bugfix for "share" passClifford Wolf2014-09-211-3/+7
* | Added "share -limit"Clifford Wolf2014-09-211-1/+13
* | Still loop bug in "share": changed assert to warningClifford Wolf2014-09-211-13/+25
* | Do not introduce new logic loops in "share"Clifford Wolf2014-09-211-6/+47
* | Assert on new logic loops in "share" passClifford Wolf2014-09-212-1/+49
* | Added "test_abcloop" commandClifford Wolf2014-09-192-0/+286
* | Initialize RTLIL::Const from std::vector<bool>Clifford Wolf2014-09-192-1/+9
* | Sorting of object names in ilang backendClifford Wolf2014-09-192-21/+49
* | Small improvements in "abc" command handle_loops() functionClifford Wolf2014-09-191-6/+9
* | Using "NOT" instead of "INV" as cell name in default abc genlib fileClifford Wolf2014-09-191-2/+2
* | Alphabetically sort port names in "show" outputClifford Wolf2014-09-191-0/+3
* | Do not run "scorr" in "abc -fast"Clifford Wolf2014-09-181-4/+4
* | Improvements in "synth" scriptClifford Wolf2014-09-181-8/+12
* | Added "abc -fast"Clifford Wolf2014-09-181-6/+31
* | Added commit count to devel version numberClifford Wolf2014-09-171-1/+1
* | Fixed $_NOR vs. $_NOR_ typo in abc.ccClifford Wolf2014-09-161-1/+1
* | Fixed $memwr/$memrd order in memory_dffClifford Wolf2014-09-161-4/+6
* | Added new CodingReadme file (replaces CodingStyle and CHECKLISTS)Clifford Wolf2014-09-163-65/+84
* | Fixed $macc simlib model for zero-configClifford Wolf2014-09-161-1/+1
* | More aggressive $macc merging in alumaccClifford Wolf2014-09-151-1/+37
* | Added the obvious optimizations to alumacc $macc generatorClifford Wolf2014-09-152-0/+61
* | Improved maccmap tree bit packingClifford Wolf2014-09-151-16/+50
* | Fixed wreduce $shiftx handlingClifford Wolf2014-09-151-1/+1
* | Fixed monitor notifications for removed cellClifford Wolf2014-09-141-0/+3
* | Added "synth" commandClifford Wolf2014-09-146-20/+174
* | Fixed techmap_wrap for techmap_celltypeClifford Wolf2014-09-141-9/+16
* | Using alumacc in techmap.vClifford Wolf2014-09-141-237/+33
* | Various fixes/cleanups in alumacc and maccmapClifford Wolf2014-09-142-2/+11
* | Added techmap_wrap attributeClifford Wolf2014-09-141-5/+28
* | alumacc fix for $pos cellsClifford Wolf2014-09-141-13/+24
* | Extract $alu cells in alumaccClifford Wolf2014-09-141-1/+296
* | Merge $macc cells in alumacc passClifford Wolf2014-09-141-1/+59
* | Basic $macc extract in alumaccClifford Wolf2014-09-141-4/+104
* | alumacc skeletonClifford Wolf2014-09-142-0/+64
* | Cleanup in wreduceClifford Wolf2014-09-141-11/+8
* | Using pkg-config to find libffiClifford Wolf2014-09-131-2/+2
* | Fixed simlib $macc model for xilinx xsimClifford Wolf2014-09-081-1/+15
* | Simplified $fa undef modelClifford Wolf2014-09-083-15/+6
* | Fixes and cleanups for blackbox.vClifford Wolf2014-09-082-70/+73
* | Added $lcu cell typeClifford Wolf2014-09-088-76/+142
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