| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Progress with new BTOR backend | Clifford Wolf | 2017-11-23 | 1 | -8/+109 |
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| * | Add skeleton for new BTOR back-end | Clifford Wolf | 2017-11-23 | 2 | -0/+216 |
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| * | Remove old BTOR back-end | Clifford Wolf | 2017-11-23 | 4 | -1174/+0 |
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| * | Accept real-valued delay values | Clifford Wolf | 2017-11-18 | 1 | -0/+1 |
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| * | Merge pull request #452 from cr1901/master | Clifford Wolf | 2017-11-18 | 1 | -4/+20 |
| |\ | | | | | Accommodate Windows-style paths during include-file processing. | ||||
| | * | Accommodate Windows-style paths during include-file processing. | William D. Jones | 2017-11-14 | 1 | -4/+20 |
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| * | | Merge pull request #453 from dh73/master | Clifford Wolf | 2017-11-18 | 14 | -9/+316 |
| |\ \ | | | | | | | Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells | ||||
| | * | | Fixed the -vout flag to -vqm in examples/intel directory | dh73 | 2017-11-14 | 4 | -4/+4 |
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| | * | | Initial Cyclone 10 support | dh73 | 2017-11-08 | 5 | -1/+308 |
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| | * | | Merge https://github.com/cliffordwolf/yosys | dh73 | 2017-11-08 | 25 | -449/+588 |
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| | * | | Organizing Speedster file names | dh73 | 2017-11-08 | 5 | -4/+4 |
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| * | | | Add "synth_ice40 -vpr" | Clifford Wolf | 2017-11-16 | 2 | -5/+29 |
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| * | | Add support for editline as replacement for readline | Clifford Wolf | 2017-11-08 | 4 | -10/+39 |
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| * | | Add "ltp" command | Clifford Wolf | 2017-10-31 | 2 | -0/+186 |
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| * | | Fix SMT2 handling of initstate in sub-modules | Clifford Wolf | 2017-10-29 | 1 | -0/+3 |
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| * | | Fix memory corruption bug in opt_rmdff | Clifford Wolf | 2017-10-26 | 1 | -0/+3 |
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| * | | Fix typo in opt_clean log message | Clifford Wolf | 2017-10-26 | 1 | -1/+1 |
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| * | | Improve smtio performance by using reader thread, not writer thread | Clifford Wolf | 2017-10-26 | 1 | -10/+30 |
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| * | | Use separate writer thread for talking to SMT solver to avoid read/write ↵ | Clifford Wolf | 2017-10-25 | 1 | -8/+23 |
| | | | | | | | | | deadlock | ||||
| * | | Improve p_* functions in smtio.py | Clifford Wolf | 2017-10-25 | 1 | -21/+19 |
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| * | | Disable OSX in .travis.yml | Clifford Wolf | 2017-10-25 | 1 | -2/+2 |
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| * | | Add ENABLE_DEBUG config flag | Clifford Wolf | 2017-10-25 | 1 | -1/+10 |
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| * | | Update ABC to hg rev f6838749f234 | Clifford Wolf | 2017-10-25 | 1 | -1/+1 |
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| * | | Remove vhdl2verilog | Clifford Wolf | 2017-10-25 | 2 | -184/+0 |
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| * | | Capsulate smt-solver read/write in separate functions | Clifford Wolf | 2017-10-25 | 1 | -8/+24 |
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| * | | Fix a bug in yosys-smtbmc in ROM handling | Clifford Wolf | 2017-10-25 | 1 | -0/+3 |
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| * | | Remove PSL example from tests/sva/ | Clifford Wolf | 2017-10-20 | 2 | -35/+1 |
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| * | | Remove all PSL support code from verific.cc | Clifford Wolf | 2017-10-20 | 1 | -179/+17 |
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| * | | Merge pull request #437 from mithro/master | Clifford Wolf | 2017-10-20 | 2 | -1/+14 |
| |\ \ | | | | | | | Adding COPYING file with license information. | ||||
| | * | | Adding COPYING file with license information. | Tim 'mithro' Ansell | 2017-10-19 | 2 | -1/+14 |
| |/ / | | | | | | | | | This allows GitHub and other tools to detect the license info. Providing a COPYING for LICENSE file is also pretty standard. | ||||
| * | | Revert 90be0d8 as it causes endless loops for some designs | Clifford Wolf | 2017-10-14 | 1 | -1/+0 |
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| * | | Add "verific -vlog-libdir" | Clifford Wolf | 2017-10-13 | 1 | -0/+12 |
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| * | | Add "verific -vlog-incdir" and "verific -vlog-define" | Clifford Wolf | 2017-10-13 | 1 | -0/+35 |
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| * | | Update Verific README | Clifford Wolf | 2017-10-13 | 1 | -0/+7 |
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| * | | Merge pull request #434 from Kmanfi/vector_fix | Clifford Wolf | 2017-10-12 | 1 | -0/+1 |
| |\ \ | | | | | | | Fix input vector for reduce cells. | ||||
| | * | | Fix input vector for reduce cells. | Kaj Tuomi | 2017-10-12 | 1 | -0/+1 |
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| * | | | Add Verific fairness/liveness support | Clifford Wolf | 2017-10-12 | 1 | -11/+32 |
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| * | | Update ABC to hg rev 6283c5d99b06 | Clifford Wolf | 2017-10-11 | 1 | -1/+1 |
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| * | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2017-10-10 | 28 | -211/+234 |
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| | * | | Rewrite ABC output to include proper net names in timing report | Clifford Wolf | 2017-10-10 | 1 | -2/+17 |
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| | * | | Add timing constraints to osu035 example | Clifford Wolf | 2017-10-10 | 3 | -2/+4 |
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| | * | | Remove some dead code | Clifford Wolf | 2017-10-10 | 1 | -15/+0 |
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| | * | | Allow $past, $stable, $rose, $fell in $global_clock blocks | Clifford Wolf | 2017-10-10 | 1 | -1/+5 |
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| | * | Add $shiftx support to verilog front-end | Clifford Wolf | 2017-10-07 | 1 | -0/+17 |
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| | * | Update ABC to hg rev 0fc1803a77c0 | Clifford Wolf | 2017-10-06 | 1 | -1/+1 |
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| | * | Clean whitespace and permissions in techlibs/intel | Larry Doolittle | 2017-10-05 | 21 | -190/+190 |
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| * | | Start work on pre-processor for Verific SVA properties | Clifford Wolf | 2017-10-10 | 1 | -10/+153 |
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| * | Improve handling of Verific errors | Clifford Wolf | 2017-10-05 | 1 | -11/+9 |
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| * | Improve Verific error handling, check VHDL static asserts | Clifford Wolf | 2017-10-04 | 1 | -11/+25 |
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| * | Add blackbox command | Clifford Wolf | 2017-10-04 | 2 | -0/+82 |
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index : iCE40/yosys | |
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