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Merge pull request #1147 from YosysHQ/clifford/fix1144
Clifford Wolf
2019-07-03
3
-82
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+26
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Fix tests/various/specify.v
Clifford Wolf
2019-07-03
2
-8
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+3
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Some cleanups in "ignore specify parser"
Clifford Wolf
2019-07-03
2
-80
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+6
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Comment out invalid syntax
Eddie Hung
2019-06-30
1
-2
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+2
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Add test from #1144, and try reading without '-specify' flag
Eddie Hung
2019-06-28
2
-0
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+16
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Improve specify dummy parser, fixes #1144
Clifford Wolf
2019-06-28
1
-2
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+9
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Merge pull request #1154 from whitequark/manual-sync-always
Clifford Wolf
2019-07-03
1
-2
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+3
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manual: explain the purpose of `sync always`.
whitequark
2019-07-02
1
-2
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+3
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Merge pull request #1150 from YosysHQ/eddie/script_from_wire
Eddie Hung
2019-07-02
3
-8
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+60
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Update test for Pass::call_on_module()
Eddie Hung
2019-07-02
1
-1
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+1
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Use Pass::call_on_module() as per @cliffordwolf comments
Eddie Hung
2019-07-02
1
-1
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+1
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Update test too
Eddie Hung
2019-07-02
1
-2
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+2
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script -select -> script -scriptwire
Eddie Hung
2019-07-02
2
-6
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+6
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Space
Eddie Hung
2019-07-01
1
-0
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+1
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Move CHANGELOG entry from yosys-0.8 to 0.9
Eddie Hung
2019-07-01
1
-7
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+1
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Merge branch 'master' into eddie/script_from_wire
Eddie Hung
2019-07-01
4
-5
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+15
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Merge branch 'master' into eddie/script_from_wire
Eddie Hung
2019-06-28
1
-1
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+1
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Try command in another module
Eddie Hung
2019-06-28
1
-0
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+3
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Add to CHANGELOG
Eddie Hung
2019-06-28
1
-0
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+6
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Support ability for "script -select" to take commands from wires
Eddie Hung
2019-06-28
1
-8
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+39
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Add test
Eddie Hung
2019-06-28
1
-0
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+17
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Merge pull request #1153 from YosysHQ/dave/fix_multi_mux
David Shah
2019-07-02
3
-3
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+25
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memory_dff: Fix checking of feedback mux input when more than one mux
David Shah
2019-07-02
3
-3
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+25
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Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi...
Clifford Wolf
2019-07-02
1
-0
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+2
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Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG
Eddie Hung
2019-07-01
1
-5
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+11
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Merge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung
2019-07-01
3
-0
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+4
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install *_nowide.lut files
Eddie Hung
2019-06-29
2
-0
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+3
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Merge pull request #1149 from gsomlo/gls-1098-abcext-fixup
Eddie Hung
2019-06-28
1
-0
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+1
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Make abc9 pass aware of optional ABCEXTERNAL override
Gabriel L. Somlo
2019-06-28
1
-0
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+1
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autotest.sh to define _AUTOTB when test_autotb
Eddie Hung
2019-06-28
1
-1
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+1
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Replace log_assert() with meaningful log_error()
Eddie Hung
2019-06-28
1
-1
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+5
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Remove peepopt call in synth_xilinx since already in synth -run coarse
Eddie Hung
2019-06-28
1
-5
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+0
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Add missing CHANGELOG entries
Eddie Hung
2019-06-28
1
-0
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+3
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Fix spacing
Eddie Hung
2019-06-28
1
-2
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+2
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Merge pull request #1098 from YosysHQ/xaig
Eddie Hung
2019-06-28
45
-247
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+3642
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Add generic __builtin_bswap32 function
Eddie Hung
2019-06-28
1
-0
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+15
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Also fix write_aiger for UB
Eddie Hung
2019-06-28
1
-26
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+26
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Fix more potential for undefined behaviour due to container invalidation
Eddie Hung
2019-06-28
1
-6
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+10
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Update synth_ice40 -device doc to be relevant for -abc9 only
Eddie Hung
2019-06-28
1
-2
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+2
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Disable boxing of ECP5 dist RAM due to regression
Eddie Hung
2019-06-28
1
-1
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+1
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Add write address to abc_scc_break of ECP5 dist RAM
Eddie Hung
2019-06-28
1
-1
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+1
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Fix DO4 typo
Eddie Hung
2019-06-28
1
-1
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+1
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Reduce diff with upstream
Eddie Hung
2019-06-27
1
-4
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+2
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Extraneous newline
Eddie Hung
2019-06-27
1
-1
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+0
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Remove noise from ice40/cells_sim.v
Eddie Hung
2019-06-27
1
-5
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+0
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Refactor for one "abc_carry" attribute on module
Eddie Hung
2019-06-27
5
-82
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+84
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung
2019-06-27
2
-0
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+19
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-27
2
-0
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+19
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Do not use Module::remove() iterator version
Eddie Hung
2019-06-27
1
-5
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+6
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Remove redundant doc
Eddie Hung
2019-06-27
1
-3
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+0
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