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| * | | | | | | | | | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
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* | | | | | | | | | Merge pull request #725 from olofk/ram4k-initClifford Wolf2018-12-161-0/+19
|\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosys
| * | | | | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosysOlof Kindgren2018-12-061-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In an initial statement, blocking assignments are normally used and e.g. verilator throws a warning if non-blocking ones are used. Yosys cannot however properly resolve the interdependencies if blocking assignments are used in the initialization of SB_RAM_40_4K and thus this has been used. This patch will change to use non-blocking assignments only for yosys
* | | | | | | | | | | Merge pull request #714 from daveshah1/abc_preserve_namingClifford Wolf2018-12-161-29/+51
|\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Proof-of-concept: preserve naming through ABC using dress
| * | | | | | | | | | | abc: Preserve naming through ABC using 'dress' commandDavid Shah2018-12-061-29/+51
| |/ / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | Merge pull request #723 from whitequark/synth_ice40_map_gatesClifford Wolf2018-12-161-0/+4
|\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | synth_ice40: split `map_gates` off `fine`
| * | | | | | | | | | | synth_ice40: split `map_gates` off `fine`.whitequark2018-12-061-0/+4
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* | | | | | | | | | | Merge pull request #722 from whitequark/rename_srcClifford Wolf2018-12-161-0/+50
|\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | rename: add -src, for inferring names from source locations
| * | | | | | | | | | | rename: add -src, for inferring names from source locations.whitequark2018-12-051-0/+50
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* | | | | | | | | | | Merge pull request #720 from whitequark/masterClifford Wolf2018-12-162-2/+2
|\ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|/ / / / / / |/| | | | | | | | | | lut2mux: handle 1-bit INIT constant in $lut cells
| * | | | | | | | | | lut2mux: handle 1-bit INIT constant in $lut cells.whitequark2018-12-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass already handles INIT constants shorter than 2^width, but that was not done for the recursion base case.
| * | | | | | | | | | opt_lut: simplify type conversion. NFC.whitequark2018-12-051-1/+1
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* | | | / / / / / / Add yosys-smtbmc support for btor witnessClifford Wolf2018-12-101-15/+100
| |_|_|/ / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | Add "yosys-smtbmc --btorwit" skeletonClifford Wolf2018-12-081-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | Fix btor init value handlingClifford Wolf2018-12-081-9/+13
| |_|/ / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | Merge pull request #727 from whitequark/opt_lutDavid Shah2018-12-073-5/+50
|\ \ \ \ \ \ \ \ | |_|/ / / / / / |/| | | | | | | opt_lut: leave intact LUTs with cascade feeding module outputs
| * | | | | | | opt_lut: leave intact LUTs with cascade feeding module outputs.whitequark2018-12-073-0/+26
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| * | | | | | | opt_lut: show original truth table for both cells.whitequark2018-12-071-2/+3
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| * | | | | | | opt_lut: add -limit option, for debugging misoptimizations.whitequark2018-12-071-3/+21
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* | | | | | | Add missing .gitignoreClifford Wolf2018-12-061-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | Bugfix in opt_expr handling of a<0 and a>=0Clifford Wolf2018-12-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | Verific updatesClifford Wolf2018-12-062-54/+1
|/ / / / / / | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #709 from smunaut/issue_708Clifford Wolf2018-12-051-1/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | Make return value of $clog2 signed
| * | | | | | Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | | | | | Merge pull request #718 from whitequark/gate2lutClifford Wolf2018-12-0512-4/+151
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs
| * | | | | | | synth_ice40: add -noabc option, to use built-in LUT techmapping.whitequark2018-12-051-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should be combined with -relut to get sensible results.
| * | | | | | | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-0510-0/+133
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| * | | | | | | Fix typo.whitequark2018-12-051-2/+2
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* | | | | | | Merge pull request #713 from Diego-HR/masterClifford Wolf2018-12-055-12/+91
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Changes in GoWin synth commands and ALU primitive support
| * | | | | | | Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-035-12/+91
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* | | | | | | | Merge pull request #712 from mmicko/anlogic-supportClifford Wolf2018-12-057-0/+1278
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Initial support for Anlogic FPGA
| * | | | | | | | Leave only real black box cellsMiodrag Milanovic2018-12-021-312/+0
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| * | | | | | | | Initial support for Anlogic FPGAMiodrag Milanovic2018-12-017-0/+1590
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* | | | | | | | Rename opt_lut.cpp to opt_lut.ccClifford Wolf2018-12-051-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | Merge pull request #717 from whitequark/opt_lutClifford Wolf2018-12-059-2/+537
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Add a new opt_lut pass, which combines inefficiently packed LUTs
| * | | | | | | | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-053-20/+166
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| * | | | | | | | opt_lut: always prefer to eliminate 1-LUTs.whitequark2018-12-051-19/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are always either buffers or inverters, and keeping the larger LUT preserves more source-level information about the design.
| * | | | | | | | opt_lut: collect and display statistics.whitequark2018-12-051-4/+33
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| * | | | | | | | opt_lut: refactor to use a worker. NFC.whitequark2018-12-051-170/+177
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| * | | | | | | | synth_ice40: add -relut option, to run ice40_unlut and opt_lut.whitequark2018-12-051-1/+13
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| * | | | | | | | opt_lut: new pass, to combine LUTs for tighter packing.whitequark2018-12-058-1/+320
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* | | | | | | | | Merge pull request #716 from whitequark/ice40_unlutClifford Wolf2018-12-053-13/+109
|\| | | | | | | | | | | | | | | | | | | | | | | | | | Extract ice40_unlut pass from ice40_opt
| * | | | | | | | Extract ice40_unlut pass from ice40_opt.whitequark2018-12-053-13/+109
|/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert them back to logic immediately. This is not desirable if the goal is to operate on $lut cells. If this is desirable, the same result as `ice40_opt -unlut` can be achieved by running simplemap and opt after ice40_unlut.
* | | | | | | | Merge pull request #719 from YosysHQ/q3k/flailing-around-trying-to-fix-osxSerge Bazanski2018-12-052-3/+2
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Fix Travis on OSX
| * | | | | | | | travis/osx: fix, use clang instead of gccSergiusz Bazanski2018-12-052-3/+2
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* | | | | | | | Fix typoClifford Wolf2018-12-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | Merge pull request #702 from smunaut/min_ce_useClifford Wolf2018-12-042-1/+50
|\ \ \ \ \ \ \ \ | |/ / / / / / / |/| | | | | | | Add option to only use DFFE is the resulting E signal would be use > N times
| * | | | | | | ice40: Add option to only use CE if it'd be use by more than X FFsSylvain Munaut2018-11-271-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | | | | | | dff2dffe: Add option for unmap to only remove DFFE with low CE signal useSylvain Munaut2018-11-271-1/+36
| |/ / / / / / | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | | | | | Merge pull request #676 from rafaeltp/masterClifford Wolf2018-12-011-10/+17
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Splits SigSpec into bits before calling check_signal_in_fanout (solves #675)
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