| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | | | Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata | Clifford Wolf | 2018-12-16 | 1 | -0/+17 | |
| |\ \ \ \ \ | | | | | | | | | | | | | memory_bram: Fix initdata bit order after shuffling | |||||
| | * | | | | | memory_bram: Fix initdata bit order after shuffling | Graham Edgecombe | 2018-12-11 | 1 | -0/+17 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases the memory_bram pass shuffles the order of the bits in a memory's RD_DATA port. Although the order of the bits in the WR_DATA and WR_EN ports is changed to match the RD_DATA port, the order of the bits in the initialization data is not. This causes reads of initialized memories to return invalid data (until the initialization data is overwritten). This commit fixes the bug by shuffling the initdata bits in exactly the same order as the RD_DATA/WR_DATA/WR_EN bits. | |||||
| * | | | | | | Merge pull request #730 from smunaut/ffssr_dont_touch | Clifford Wolf | 2018-12-16 | 1 | -0/+3 | |
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | ice40: Honor the "dont_touch" attribute in FFSSR pass | |||||
| | * | | | | | | ice40: Honor the "dont_touch" attribute in FFSSR pass | Sylvain Munaut | 2018-12-08 | 1 | -0/+3 | |
| | |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is useful if you want to place FF manually ... can't merge SR in those because it might make the manual placement invalid Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
| * | | | | | | Merge pull request #729 from whitequark/write_verilog_initial | Clifford Wolf | 2018-12-16 | 1 | -0/+2 | |
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | write_verilog: correctly map RTLIL `sync init` | |||||
| | * | | | | | | write_verilog: correctly map RTLIL `sync init`. | whitequark | 2018-12-07 | 1 | -0/+2 | |
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| * | | | | | | Merge pull request #725 from olofk/ram4k-init | Clifford Wolf | 2018-12-16 | 1 | -0/+19 | |
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosys | |||||
| | * | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosys | Olof Kindgren | 2018-12-06 | 1 | -0/+19 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In an initial statement, blocking assignments are normally used and e.g. verilator throws a warning if non-blocking ones are used. Yosys cannot however properly resolve the interdependencies if blocking assignments are used in the initialization of SB_RAM_40_4K and thus this has been used. This patch will change to use non-blocking assignments only for yosys | |||||
| * | | | | | | | Merge pull request #714 from daveshah1/abc_preserve_naming | Clifford Wolf | 2018-12-16 | 1 | -29/+51 | |
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | Proof-of-concept: preserve naming through ABC using dress | |||||
| | * | | | | | | | abc: Preserve naming through ABC using 'dress' command | David Shah | 2018-12-06 | 1 | -29/+51 | |
| | |/ / / / / / | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | | | Merge pull request #723 from whitequark/synth_ice40_map_gates | Clifford Wolf | 2018-12-16 | 1 | -0/+4 | |
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | synth_ice40: split `map_gates` off `fine` | |||||
| | * | | | | | | | synth_ice40: split `map_gates` off `fine`. | whitequark | 2018-12-06 | 1 | -0/+4 | |
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| * | | | | | | | Merge pull request #722 from whitequark/rename_src | Clifford Wolf | 2018-12-16 | 1 | -0/+50 | |
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | rename: add -src, for inferring names from source locations | |||||
| | * | | | | | | | rename: add -src, for inferring names from source locations. | whitequark | 2018-12-05 | 1 | -0/+50 | |
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| * | | | | | | | Merge pull request #720 from whitequark/master | Clifford Wolf | 2018-12-16 | 2 | -2/+2 | |
| |\ \ \ \ \ \ \ | |_|_|_|_|/ / |/| | | | | | | lut2mux: handle 1-bit INIT constant in $lut cells | |||||
| | * | | | | | | lut2mux: handle 1-bit INIT constant in $lut cells. | whitequark | 2018-12-05 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass already handles INIT constants shorter than 2^width, but that was not done for the recursion base case. | |||||
| | * | | | | | | opt_lut: simplify type conversion. NFC. | whitequark | 2018-12-05 | 1 | -1/+1 | |
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| * | | | / / | Add yosys-smtbmc support for btor witness | Clifford Wolf | 2018-12-10 | 1 | -15/+100 | |
| | |_|_|/ / |/| | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Add "yosys-smtbmc --btorwit" skeleton | Clifford Wolf | 2018-12-08 | 1 | -1/+19 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Fix btor init value handling | Clifford Wolf | 2018-12-08 | 1 | -9/+13 | |
| | |_|/ / |/| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | Merge pull request #727 from whitequark/opt_lut | David Shah | 2018-12-07 | 3 | -5/+50 | |
| |\ \ \ \ | |_|/ / |/| | | | opt_lut: leave intact LUTs with cascade feeding module outputs | |||||
| | * | | | opt_lut: leave intact LUTs with cascade feeding module outputs. | whitequark | 2018-12-07 | 3 | -0/+26 | |
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| | * | | | opt_lut: show original truth table for both cells. | whitequark | 2018-12-07 | 1 | -2/+3 | |
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| | * | | | opt_lut: add -limit option, for debugging misoptimizations. | whitequark | 2018-12-07 | 1 | -3/+21 | |
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| * | | | Add missing .gitignore | Clifford Wolf | 2018-12-06 | 1 | -0/+8 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Bugfix in opt_expr handling of a<0 and a>=0 | Clifford Wolf | 2018-12-06 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Verific updates | Clifford Wolf | 2018-12-06 | 2 | -54/+1 | |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #709 from smunaut/issue_708 | Clifford Wolf | 2018-12-05 | 1 | -1/+1 | |
| |\ \ | | | | | | | Make return value of $clog2 signed | |||||
| | * | | Make return value of $clog2 signed | Sylvain Munaut | 2018-11-24 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
| * | | | Merge pull request #718 from whitequark/gate2lut | Clifford Wolf | 2018-12-05 | 12 | -4/+151 | |
| |\ \ \ | | | | | | | | | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs | |||||
| | * | | | synth_ice40: add -noabc option, to use built-in LUT techmapping. | whitequark | 2018-12-05 | 1 | -2/+16 | |
| | | | | | | | | | | | | | | | | | This should be combined with -relut to get sensible results. | |||||
| | * | | | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. | whitequark | 2018-12-05 | 10 | -0/+133 | |
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| | * | | | Fix typo. | whitequark | 2018-12-05 | 1 | -2/+2 | |
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| * | | | Merge pull request #713 from Diego-HR/master | Clifford Wolf | 2018-12-05 | 5 | -12/+91 | |
| |\ \ \ | | | | | | | | | Changes in GoWin synth commands and ALU primitive support | |||||
| | * | | | Changes in GoWin synth commands and ALU primitive support | Diego H | 2018-12-03 | 5 | -12/+91 | |
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| * | | | | Merge pull request #712 from mmicko/anlogic-support | Clifford Wolf | 2018-12-05 | 7 | -0/+1278 | |
| |\ \ \ \ | | | | | | | | | | | Initial support for Anlogic FPGA | |||||
| | * | | | | Leave only real black box cells | Miodrag Milanovic | 2018-12-02 | 1 | -312/+0 | |
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| | * | | | | Initial support for Anlogic FPGA | Miodrag Milanovic | 2018-12-01 | 7 | -0/+1590 | |
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| * | | | | Rename opt_lut.cpp to opt_lut.cc | Clifford Wolf | 2018-12-05 | 1 | -0/+0 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | Merge pull request #717 from whitequark/opt_lut | Clifford Wolf | 2018-12-05 | 9 | -2/+537 | |
| |\ \ \ \ | | | | | | | | | | | Add a new opt_lut pass, which combines inefficiently packed LUTs | |||||
| | * | | | | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. | whitequark | 2018-12-05 | 3 | -20/+166 | |
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| | * | | | | opt_lut: always prefer to eliminate 1-LUTs. | whitequark | 2018-12-05 | 1 | -19/+41 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | These are always either buffers or inverters, and keeping the larger LUT preserves more source-level information about the design. | |||||
| | * | | | | opt_lut: collect and display statistics. | whitequark | 2018-12-05 | 1 | -4/+33 | |
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| | * | | | | opt_lut: refactor to use a worker. NFC. | whitequark | 2018-12-05 | 1 | -170/+177 | |
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| | * | | | | synth_ice40: add -relut option, to run ice40_unlut and opt_lut. | whitequark | 2018-12-05 | 1 | -1/+13 | |
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| | * | | | | opt_lut: new pass, to combine LUTs for tighter packing. | whitequark | 2018-12-05 | 8 | -1/+320 | |
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| * | | | | | Merge pull request #716 from whitequark/ice40_unlut | Clifford Wolf | 2018-12-05 | 3 | -13/+109 | |
| |\| | | | | | | | | | | | | | | Extract ice40_unlut pass from ice40_opt | |||||
| | * | | | | Extract ice40_unlut pass from ice40_opt. | whitequark | 2018-12-05 | 3 | -13/+109 | |
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert them back to logic immediately. This is not desirable if the goal is to operate on $lut cells. If this is desirable, the same result as `ice40_opt -unlut` can be achieved by running simplemap and opt after ice40_unlut. | |||||
| * | | | | Merge pull request #719 from YosysHQ/q3k/flailing-around-trying-to-fix-osx | Serge Bazanski | 2018-12-05 | 2 | -3/+2 | |
| |\ \ \ \ | | | | | | | | | | | Fix Travis on OSX | |||||
| | * | | | | travis/osx: fix, use clang instead of gcc | Sergiusz Bazanski | 2018-12-05 | 2 | -3/+2 | |
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index : iCE40/yosys | |
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