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* Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-186-9/+248
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* Update ABC to git rev 14d985aClifford Wolf2018-10-181-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-1811-21/+649
|\ | | | | Support for SystemVerilog interfaces and modports
| * Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
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| * Documentation improvements etc.Ruben Undheim2018-10-135-38/+77
| | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
| * Fix build error with clangRuben Undheim2018-10-121-1/+1
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| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-128-14/+121
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| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-1210-21/+501
| | | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | Merge pull request #657 from mithro/xilinx-vprClifford Wolf2018-10-181-3/+2
|\ \ | | | | | | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
| * | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
| |/ | | | | | | | | Then if targeting vpr map all the Xilinx specific LUTs back into generic Yosys LUTs.
* | Merge pull request #664 from tklam/ignore-verilog-protectClifford Wolf2018-10-181-0/+3
|\ \ | | | | | | Ignore protect endprotect
| * | ignore protect endprotectargama2018-10-161-0/+3
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* | Update ABC to git rev c5b48bbClifford Wolf2018-10-171-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Minor code cleanups in liberty front-endClifford Wolf2018-10-171-16/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #660 from tklam/parse-liberty-detect-ff-latchClifford Wolf2018-10-171-0/+17
|\ \ | | | | | | Handling ff/latch in liberty files
| * | detect ff/latch before processing other nodesargama2018-10-141-0/+17
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* | Merge pull request #663 from aman-goel/masterClifford Wolf2018-10-171-32/+51
|\ \ | | | | | | Update to .smv backend
| * | Minor updateAman Goel2018-10-152-3/+3
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| * | Update to .smv backendAman Goel2018-10-012-35/+54
| | | | | | | | | | | | Splitting VAR and ASSIGN into IVAR, VAR, DEFINE and ASSIGN. This allows better handling by nuXmv for post-processing (since now only state variables are listed under VAR).
| * | Merge pull request #4 from YosysHQ/masterAman Goel2018-10-0131-107/+529
| |\ \ | | | | | | | | Merge with official repo
* | \ \ Merge pull request #658 from daveshah1/ecp5_bramClifford Wolf2018-10-179-20/+371
|\ \ \ \ | | | | | | | | | | ECP5 BRAM inference
| * | | | ecp5: Disable LSR inversionDavid Shah2018-10-162-21/+21
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | BRAM improvementsDavid Shah2018-10-121-11/+16
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | ecp5: Adding BRAM maps for all size optionsDavid Shah2018-10-101-1/+64
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | ecp5: First BRAM type maps successfullyDavid Shah2018-10-108-10/+76
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | ecp5: Script for BRAM IO connectionsDavid Shah2018-10-104-64/+115
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | ecp5: Adding BRAM initialisation and configDavid Shah2018-10-095-0/+73
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | ecp5: Add blackbox for DP16KDDavid Shah2018-10-051-0/+93
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge pull request #641 from tklam/masterClifford Wolf2018-10-171-0/+69
|\ \ \ \ \ | | | | | | | | | | | | Fix issue #639
| * | | | | stop check_signal_in_fanout from traversing FFstklam2018-10-131-2/+2
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| * | | | | stop check_signal_in_fanout from traversing FFstklam2018-10-131-1/+12
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| * | | | | Merge branch 'master' of https://github.com/YosysHQ/yosystklam2018-10-136-17/+61
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| * | | | | Merge branch 'master' of https://github.com/YosysHQ/yosystklam2018-10-034-7/+12
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| * | | | | | fix bug: pass by referencetklam2018-09-261-1/+1
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| * | | | | | Fix issue #639TK Lam2018-09-261-0/+58
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* | | | | | | Merge pull request #638 from udif/pr_reg_wire_errorClifford Wolf2018-10-171-0/+12
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Fix issue #630
| * | | | | | | Fixed issue #630 by fixing a minor typo in the previous commitUdi Finkelstein2018-09-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (as well as a non critical minor code optimization)
| * | | | | | | Merge branch 'master' into pr_reg_wire_errorUdi Finkelstein2018-09-18226-1397/+5434
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| * | | | | | | | Fixed remaining cases where we check fo wire reg/wire incorrect assignmentsUdi Finkelstein2018-09-181-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
* | | | | | | | | We have 2018 nowClifford Wolf2018-10-162-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | After release is before releaseClifford Wolf2018-10-162-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | Merge branch 'yosys-0.8-rc'Clifford Wolf2018-10-162-141/+1201
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| * | | | | | | | Yosys 0.8Clifford Wolf2018-10-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | Update command reference manualClifford Wolf2018-10-161-140/+1200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | Improve Verific importer blackbox handlingClifford Wolf2018-10-071-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | Merge pull request #651 from ARandomOWL/stdcells_fixClifford Wolf2018-10-051-1/+1
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | Fix IdString M in setup_stdcells()
| * | | | | | | | | Fix IdString M in setup_stdcells()Adrian Wheeldon2018-10-041-1/+1
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* | | | | | | | | Add "write_edif -attrprop"Clifford Wolf2018-10-051-11/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | Merge pull request #654 from mithro/patch-1Clifford Wolf2018-10-051-1/+1
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | Fix misspelling in issue_template.md
| * | | | | | | | | Fix misspelling in issue_template.mdTim Ansell2018-10-041-1/+1
| | |_|_|_|_|/ / / | |/| | | | | | | | | | | | | | | | It's been bugging me :-P
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