aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* flatten: simplify. NFC.whitequark2020-06-041-7/+3
| | | | Remove redundant sigmaps.
* flatten: simplify.whitequark2020-06-041-35/+0
| | | | | Flattening does not benefit from topologically sorting cells within a module when processing them.
* flatten: simplify. NFC.whitequark2020-06-041-11/+4
| | | | | Flatten is non-recursive and doesn't need to keep track of handled cells.
* flatten: simplify. NFC.whitequark2020-06-041-6/+4
| | | | Flattening always does "non-recursive" mapping.
* flatten: simplify. NFC.whitequark2020-06-041-73/+39
| | | | The `celltypeMap` always maps `x` to `{x}`.
* flatten: simplify. NFC.whitequark2020-06-041-8/+8
| | | | The `design` and `map` designs are always the same when flattening.
* RTLIL: factor out RTLIL::Module::addMemory. NFC.whitequark2020-06-044-14/+16
|
* flatten: rename techmap-related stuff. NFC.whitequark2020-06-041-16/+16
|
* techmap, flatten: remove dead options.whitequark2020-06-042-928/+212
| | | | | | After splitting the passes, some options can never be activated, and most conditions involving them become dead. Remove them, and also all of the newly dead code.
* flatten: split from techmap.whitequark2020-06-033-93/+1149
| | | | | | | Although the two passes started out very similar, they diverged over time and now have little in common. Moreover, `techmap` is extremely complex while `flatten` does not have to be, and this complexity interferes with improving `flatten`.
* Merge pull request #2104 from whitequark/simplify-techmapwhitequark2020-06-033-40/+8
|\ | | | | techmap: simplify
| * techmap: remove dead variable. NFC.whitequark2020-06-031-1/+0
| |
| * techmap: use C++11 default member initializers. NFC.whitequark2020-06-021-16/+6
| |
| * techmap: simplify.whitequark2020-06-021-7/+1
| | | | | | | | `rewrite_filename` is already called in `Frontend::extra_args`.
| * techmap: use +/techmap.v instead of an ad-hoc code generator.whitequark2020-06-023-16/+1
|/
* Merge pull request #2102 from YosysHQ/tests_fixclairexen2020-06-021-1/+2
|\ | | | | allow range for mux test
| * allow range for mux testMiodrag Milanovic2020-06-011-1/+2
| |
* | Merge pull request #2101 from YosysHQ/mmicko/verific_asymmetricclairexen2020-06-021-6/+1
|\ \ | |/ |/| Support asymmetric memories for verific frontend
| * Support asymmetric memories for verific frontendMiodrag Milanovic2020-06-011-6/+1
|/
* Merge pull request #1862 from boqwxp/cleanup_techmapclairexen2020-05-315-153/+169
|\ | | | | Clean up `passes/techmap/techmap.cc`
| * kernel: Try an order-independent approach to hashing `dict`.Alberto Gonzalez2020-05-191-5/+3
| | | | | | | | | | Co-Authored-By: David Shah <dave@ds0.me> Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * kernel: Ensure `dict` always hashes to the same value given the same contents.Alberto Gonzalez2020-05-141-3/+6
| |
| * kernel: Re-implement `dict` hash code as a `dict` member function instead of ↵Alberto Gonzalez2020-05-141-20/+14
| | | | | | | | a specialized template for `hash_ops`.
| * techmap: Replace naughty `const_cast<>()`s.Alberto Gonzalez2020-05-141-2/+4
| | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * techmap: Replace pseudo-private member usage with the range accessor ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | function and some naughty `const_cast<>()`s.
| * techmap: sort celltypeMap as it determines techmap orderEddie Hung2020-05-141-1/+5
| |
| * Replace `std::set`s using custom comparators with `pool`.Alberto Gonzalez2020-05-141-4/+4
| | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * techmap: prefix special wires with backslash for use as IdStringEddie Hung2020-05-143-12/+14
| |
| * Further clean up `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-5/+6
| | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * Use `emplace()` for more efficient insertion into various `dict`s.Alberto Gonzalez2020-05-141-8/+8
| |
| * Build constant bits directly rather than constructing an object and copying ↵Alberto Gonzalez2020-05-141-2/+5
| | | | | | | | its bits.
| * Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.Alberto Gonzalez2020-05-141-2/+2
| |
| * Use `emplace()` rather than `insert()`.Alberto Gonzalez2020-05-141-1/+1
| |
| * Clean up pseudo-private member usage and ensure range iteration uses ↵Alberto Gonzalez2020-05-141-17/+17
| | | | | | | | references where possible to avoid unnecessary copies.
| * Clean up extraneous buffer.Alberto Gonzalez2020-05-141-5/+2
| |
| * Replace `std::map` with `dict` for `unique_bit_id`.Alberto Gonzalez2020-05-141-1/+1
| |
| * Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | `cellbits_to_tplbits`.
| * Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | | | | | `outbit_to_cell`.
| * Replace `std::map` with `dict` for `TechmapWires` type.Alberto Gonzalez2020-05-141-1/+1
| |
| * Replace `std::map` with `dict` for `celltypeMap`.Alberto Gonzalez2020-05-141-3/+3
| |
| * Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.Alberto Gonzalez2020-05-141-4/+4
| |
| * Replace `std::map` with `dict` for `positional_ports`.Alberto Gonzalez2020-05-141-1/+1
| |
| * Add specialized `hash()` for type `dict` and use a `dict` instead of a ↵Alberto Gonzalez2020-05-143-10/+25
| | | | | | | | `std::map` for `techmap_cache` and `techmap_do_cache`.
| * Replace `std::map` with `dict` for `simplemap_mappers`.Alberto Gonzalez2020-05-143-5/+5
| |
| * Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-10/+10
| |
| * Replace `std::string` and `RTLIL::IdString` with `IdString` in ↵Alberto Gonzalez2020-05-141-21/+21
| | | | | | | | | | | | `passes/techmap/techmap.cc`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * Do not modify design modules while iterating over `modules()`.Alberto Gonzalez2020-05-141-1/+4
| | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * Clean up pseudo-private member usage, superfluous `std::vector` ↵Alberto Gonzalez2020-05-141-76/+70
| | | | | | | | instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
* | Merge pull request #2081 from YosysHQ/eddie/blackbox_astEddie Hung2020-05-301-25/+1
|\ \ | | | | | | blackbox: use Module::makeblackbox() method
| * | blackbox: re-use existing Module::makeblackbox() methodEddie Hung2020-05-251-25/+1
| | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 14:47:26 +0000