| Commit message (Expand) | Author | Age | Files | Lines | ||
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| * | | | | | | | | | | | | | | | | | Merge pull request #928 from litghost/add_xc7_sim_models | Eddie Hung | 2019-04-12 | 3 | -41/+60 | |
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| | * | | | | | | | | | | | | | | | | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 3 | -52/+14 | |
| | * | | | | | | | | | | | | | | | | | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 | |
| | * | | | | | | | | | | | | | | | | | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 | |
| * | | | | | | | | | | | | | | | | | | Merge pull request #933 from dh73/master | Clifford Wolf | 2019-04-12 | 1 | -3/+9 | |
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| | * | | | | | | | | | | | | | | | | | | Fixing issues in CycloneV cell sim | Diego | 2019-04-11 | 1 | -3/+9 | |
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| * | | | | | | | | | | | | | | | | | | Merge pull request #932 from YosysHQ/eddie/fixdlatch | Clifford Wolf | 2019-04-12 | 2 | -3/+4 | |
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| | * | | | | | | | | | | | | | | | | Add default entry to testcase | Eddie Hung | 2019-04-11 | 1 | -2/+3 | |
| | * | | | | | | | | | | | | | | | | Recognise default entry in case even if all cases covered (#931) | Eddie Hung | 2019-04-11 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | | synth_* with -retime option now calls abc with -D 1 as well | Eddie Hung | 2019-04-10 | 11 | -15/+15 | |
| | * | | | | | | | | | | | | | | | Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen" | Eddie Hung | 2019-04-10 | 1 | -2/+0 | |
| | * | | | | | | | | | | | | | | | Revert ""&nf -D 0" fails => use "-D 1" instead" | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/fix_retime | Eddie Hung | 2019-04-10 | 2 | -4/+5 | |
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| * | | | | | | | | | | | | | | | Fix a few typos | Eddie Hung | 2019-04-08 | 1 | -3/+3 | |
| * | | | | | | | | | | | | | | | Merge pull request #919 from YosysHQ/multiport_transp | Clifford Wolf | 2019-04-08 | 1 | -1/+2 | |
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| | * | | | | | | | | | | | | | | memory_bram: Fix multiport make_transp | David Shah | 2019-04-07 | 1 | -1/+2 | |
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| | * | | | | | | | | | | | | | Add retime test | Eddie Hung | 2019-04-05 | 1 | -0/+6 | |
| | * | | | | | | | | | | | | | Fix S0 -> S1 | Eddie Hung | 2019-04-05 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | Move techamp t:$_DFF_?N? to before abc call | Eddie Hung | 2019-04-05 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | Retry | Eddie Hung | 2019-04-05 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | "&nf -D 0" fails => use "-D 1" instead | Eddie Hung | 2019-04-05 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | Resolve @daveshah1 comment, update synth_xilinx help | Eddie Hung | 2019-04-05 | 2 | -7/+9 | |
| | * | | | | | | | | | | | | synth_xilinx to techmap FFs after abc call, otherwise -retime fails | Eddie Hung | 2019-04-05 | 1 | -3/+3 | |
| | * | | | | | | | | | | | | abc -dff now implies "-D 0" otherwise retiming doesn't happen | Eddie Hung | 2019-04-05 | 1 | -0/+2 | |
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| * | | | | | | | | | | | | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 5 | -3/+39 | |
| * | | | | | | | | | | | | Added missing argument checking to "mutate" command | Clifford Wolf | 2019-04-04 | 1 | -0/+32 | |
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| * | | | | | | | | | | | Merge pull request #913 from smunaut/fix_proc_mux | Eddie Hung | 2019-04-03 | 1 | -1/+1 | |
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| | * | | | | | | | | | | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx | Sylvain Munaut | 2019-04-03 | 1 | -1/+1 | |
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| * | | | | | | | | | | Merge pull request #912 from YosysHQ/bram_addr_en | Clifford Wolf | 2019-04-03 | 1 | -0/+2 | |
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| | * | | | | | | | | | | memory_bram: Consider read enable for address expansion register | David Shah | 2019-04-02 | 1 | -0/+2 | |
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| * | | | | | | | | | | Merge pull request #910 from ucb-bar/memupdates | Clifford Wolf | 2019-04-03 | 1 | -30/+173 | |
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| | * | | | | | | | | | Refine memory support to deal with general Verilog memory definitions. | Jim Lawson | 2019-04-01 | 1 | -30/+173 | |
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| * | | | | | | | | | Merge pull request #895 from YosysHQ/pmux2shiftx | Eddie Hung | 2019-04-02 | 1 | -0/+28 | |
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| | * | | | | | | | | Create one $shiftx per bit in width | Eddie Hung | 2019-03-25 | 1 | -10/+17 | |
| | * | | | | | | | | Add a pmux-to-shiftx optimisation to proc_mux | Eddie Hung | 2019-03-23 | 1 | -0/+21 | |
| * | | | | | | | | | Merge pull request #907 from YosysHQ/clifford/fix906 | Clifford Wolf | 2019-03-30 | 1 | -0/+2 | |
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| | * | | | | | | | | Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 | Clifford Wolf | 2019-03-29 | 1 | -0/+2 | |
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| * | | | | | | | | Merge pull request #901 from trcwm/libertyfixes | Clifford Wolf | 2019-03-28 | 4 | -9/+151 | |
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| | * | | | | | | | | Liberty file parser now accepts superfluous ; | Niels Moseley | 2019-03-27 | 1 | -1/+1 | |
| | * | | | | | | | | Liberty file parser now accepts superfluous ; | Niels Moseley | 2019-03-27 | 1 | -1/+1 | |
| | * | | | | | | | | Liberty file parser now accepts superfluous ; | Niels Moseley | 2019-03-27 | 4 | -9/+151 | |
| * | | | | | | | | | Merge pull request #903 from YosysHQ/bram_reset_transp | Clifford Wolf | 2019-03-28 | 1 | -0/+1 | |
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| | * | | | | | | | | memory_bram: Reset make_transp when growing read ports | David Shah | 2019-03-27 | 1 | -0/+1 | |
| * | | | | | | | | | Add "read -verific" and "read -noverific" | Clifford Wolf | 2019-03-27 | 1 | -6/+28 | |
| * | | | | | | | | | Add "rename -output" | Clifford Wolf | 2019-03-27 | 1 | -3/+23 | |
| * | | | | | | | | | Improve "rename" help message | Clifford Wolf | 2019-03-27 | 1 | -0/+6 | |
| * | | | | | | | | | Add "cutpoint -undef" | Clifford Wolf | 2019-03-26 | 1 | -10/+14 | |
| * | | | | | | | | | Add "hdlname" attribute | Clifford Wolf | 2019-03-26 | 2 | -0/+5 | |
| * | | | | | | | | | Fix "verific -extnets" for more complex situations | Clifford Wolf | 2019-03-26 | 2 | -15/+93 | |
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| * | | | | | | | | Add "cutpoint" pass | Clifford Wolf | 2019-03-25 | 2 | -0/+165 | |
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