| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx: Add SRLC16E primitive. | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+21 |
| * | Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap | Eddie Hung | 2019-08-27 | 16 | -223/+1075 |
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| | * | improve clkbuf_inhibit propagation upwards through hierarchy | Marcin Kościelnicki | 2019-08-27 | 2 | -6/+45 |
| | * | Improve tests to check that clkbuf is connected to expected | Eddie Hung | 2019-08-26 | 1 | -6/+21 |
| | * | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 8 | -60/+405 |
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| | * \ | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| | * \ \ | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 3 | -18/+36 |
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| | * | | | | Check clkbuf_inhibit=1 is ignored for custom selection | Eddie Hung | 2019-08-23 | 1 | -0/+1 |
| | * | | | | clkbufmap to only check clkbuf_inhibit if no selection given | Eddie Hung | 2019-08-23 | 1 | -5/+18 |
| | * | | | | Add simple clkbufmap tests | Eddie Hung | 2019-08-23 | 1 | -0/+52 |
| | * | | | | tests/techmap/run-test.sh to cope with *.ys | Eddie Hung | 2019-08-23 | 2 | -7/+18 |
| | * | | | | Mention clkbuf_inhibit can be overridden | Eddie Hung | 2019-08-23 | 1 | -7/+8 |
| | * | | | | Review comment from @cliffordwolf | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
| | * | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 146 | -1486/+4373 |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-16 | 57 | -3403/+3432 |
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| | * | | | | | | README updates | Marcin Kościelnicki | 2019-08-13 | 1 | -0/+14 |
| | * | | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 8 | -311/+546 |
| | * | | | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 2 | -3/+5 |
| | * | | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 4 | -47/+34 |
| | * | | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 10 | -93/+577 |
| * | | | | | | | Add "make bumpversion" | Clifford Wolf | 2019-08-27 | 2 | -0/+4 |
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| * | | | | | | Remove dupe in CHANGELOG, missing end quote | Eddie Hung | 2019-08-26 | 1 | -2/+1 |
| * | | | | | | Merge tag 'yosys-0.9' | Clifford Wolf | 2019-08-26 | 2 | -11/+107 |
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| | * | | | | | | Yosys 0.9 | Clifford Wolf | 2019-08-26 | 1 | -1/+1 |
| | * | | | | | | Revert earliest to gcc-4.8, compile iverilog with default compiler | Eddie Hung | 2019-08-23 | 2 | -3/+3 |
| | * | | | | | | Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!" | Eddie Hung | 2019-08-23 | 1 | -5/+3 |
| | * | | | | | | Remove .0 from clang-8.0 | Eddie Hung | 2019-08-23 | 1 | -2/+2 |
| | * | | | | | | Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?! | Eddie Hung | 2019-08-23 | 1 | -3/+5 |
| | * | | | | | | bionic -> xenial as its on whitelist | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
| | * | | | | | | Bump gcc from 4.8 to 4.9 as undefined reference | Eddie Hung | 2019-08-23 | 1 | -35/+7 |
| | * | | | | | | Make macOS depenency clear | Miodrag Milanovic | 2019-08-23 | 1 | -2/+5 |
| | * | | | | | | do not require boost if pyosys is not used | Miodrag Milanovic | 2019-08-22 | 1 | -0/+2 |
| | * | | | | | | require tcl-tk in Brewfile | Chris Shucksmith | 2019-08-22 | 1 | -0/+1 |
| | * | | | | | | Bump year in copyright notice | Clifford Wolf | 2019-08-22 | 3 | -3/+3 |
| | * | | | | | | Visual Studio build fix | Miodrag Milanovic | 2019-08-02 | 1 | -0/+1 |
| | * | | | | | | Fix linking issue for new mxe and pthread | Miodrag Milanovic | 2019-08-02 | 1 | -1/+2 |
| | * | | | | | | Fix yosys linking for mxe | Miodrag Milanovic | 2019-08-02 | 1 | -1/+1 |
| | * | | | | | | New mxe hacks needed to support 2ca237e | Miodrag Milanovic | 2019-08-02 | 1 | -0/+4 |
| | * | | | | | | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-02 | 8 | -17/+20 |
| | * | | | | | | Update CHANGELOG | David Shah | 2019-07-26 | 1 | -10/+101 |
| | * | | | | | | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position | Clifford Wolf | 2019-07-09 | 1 | -3/+2 |
| | * | | | | | | Update CHANGELOG | David Shah | 2019-07-09 | 1 | -0/+1 |
| | * | | | | | | Merge pull request #1163 from whitequark/more-case-attrs | Clifford Wolf | 2019-07-09 | 3 | -16/+28 |
| | * | | | | | | Merge pull request #1162 from whitequark/rtlil-case-attrs | Clifford Wolf | 2019-07-09 | 3 | -5/+15 |
| | * | | | | | | Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire | Clifford Wolf | 2019-07-09 | 1 | -0/+3 |
| | * | | | | | | Merge pull request #1147 from YosysHQ/clifford/fix1144 | Clifford Wolf | 2019-07-09 | 3 | -82/+26 |
| | * | | | | | | Merge pull request #1154 from whitequark/manual-sync-always | Clifford Wolf | 2019-07-09 | 1 | -2/+3 |
| | * | | | | | | Merge pull request #1153 from YosysHQ/dave/fix_multi_mux | David Shah | 2019-07-09 | 3 | -3/+25 |
| | * | | | | | | Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi... | Clifford Wolf | 2019-07-09 | 1 | -0/+2 |
| | * | | | | | | autotest.sh to define _AUTOTB when test_autotb | Eddie Hung | 2019-07-09 | 1 | -1/+1 |
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index : iCE40/yosys | |
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