aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* - libs/ezsat/ezminisat.cc: use sigemptyset() to clear sig_action.sa_mask; us...Siesh1oo2014-03-101-2/+2
* - Makefile: fix typo in LDFLAGS: obviously -L, not -I is required hereSiesh1oo2014-03-101-1/+1
* - Makefile: export PATH=${DESTDIR}/bin:$(PATH) and (DY)LD_LIBRARY_PATH, to m...Siesh1oo2014-03-101-2/+6
* - frontends/vhdl2verilog/vhdl2verilog.cc, passes/abc/abc.cc: #include <climi...Siesh1oo2014-03-102-0/+2
* - Makefile, techlibs/common/Makefile.inc: call GNU sed instead of BSD sed on...Siesh1oo2014-03-102-3/+5
* - libs/ezsat/ezminisat.cc: use POSIX.2001 sigaction() instead on non-portabl...Siesh1oo2014-03-101-4/+8
* - Makefile, kernel/posix_compatibility.h/.cc: provide POSIX.2008 fake implem...Siesh1oo2014-03-104-10/+211
* - README: fix typo in sed-command for minisat-include fix.Siesh1oo2014-03-101-1/+1
* - frontends/vhdl2verilog/vhdl2verilog.cc: #include <cerrno> for errno; use P...Siesh1oo2014-03-101-4/+11
* - kernel/register.cc: need to #include <cerrno> or errno.h for errno.Siesh1oo2014-03-101-0/+1
* - kernel/driver.cc: need to #include <cerrno> or errno.h for errno.Siesh1oo2014-03-101-0/+1
* - kernel/log.h: add rusage()-based fallback for systems without clock_gettim...Siesh1oo2014-03-101-0/+16
* - libs/ezsat/ezsat.cc: need to #include <cmath> or math.h for math functions.Siesh1oo2014-03-101-1/+2
* - passes/abc/abc.cc: #include <cerrno> for errno; use POSIX getcwd() for por...Siesh1oo2014-03-101-2/+6
* - passes/techmap/dfflibmap.cc, passes/fsm/fsm_recode.cc, passes/cmds/select....Siesh1oo2014-03-103-1/+4
* Fixed a typo in RTLIL::Module::addReduce...Clifford Wolf2014-03-101-5/+5
* Improved verific command (added support for some operators)Clifford Wolf2014-03-101-2/+160
* Improvements in verific commandClifford Wolf2014-03-101-59/+39
* Added RTLIL::Module::add... helper methodsClifford Wolf2014-03-102-0/+293
* Added "verific" commandClifford Wolf2014-03-093-2/+501
* Fixed dumping of timing() { .. } block in libparseClifford Wolf2014-03-091-2/+3
* Verbose reading of liberty and constr files in ABC passClifford Wolf2014-03-091-2/+2
* Fixed bug in freduce commandClifford Wolf2014-03-071-0/+30
* Some minor code cleanups in freduce commandClifford Wolf2014-03-071-5/+5
* Bugfix in ilang frontend autoidx recoveryClifford Wolf2014-03-071-2/+2
* Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-071-18/+17
* Added freduce -dumpClifford Wolf2014-03-061-1/+24
* Added freduce -stopClifford Wolf2014-03-061-3/+18
* Fixed gcc compiler warningClifford Wolf2014-03-061-1/+2
* Fixed undef handling in opt_reduceClifford Wolf2014-03-061-2/+2
* Fixes for improved techmap of shifts with large B inputsClifford Wolf2014-03-061-8/+8
* Fixed use of frozen literals in SatGenClifford Wolf2014-03-061-3/+2
* Strictly zero-extend unsigned A-inputs of shift operations in techmapClifford Wolf2014-03-061-4/+4
* Added techmap -max_iter optionClifford Wolf2014-03-061-0/+10
* Improved techmap of shift with wide B inputsClifford Wolf2014-03-061-13/+37
* Strictly zero-extend unsigned A-inputs of shift operationsClifford Wolf2014-03-062-3/+3
* Switched to EZMINISAT_SIMPSOLVER as default SAT solverClifford Wolf2014-03-051-1/+1
* Include id2ast pointers when dumping ASTClifford Wolf2014-03-051-0/+6
* Fixed merging of compatible wire decls in AST frontendClifford Wolf2014-03-051-1/+4
* Bugfix in recursive AST simplificationClifford Wolf2014-03-051-10/+22
* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-031-2/+2
* ezSAT: Added frozen_literal() APIClifford Wolf2014-03-032-0/+16
* ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressionsClifford Wolf2014-03-032-8/+23
* Added ezSAT::eliminated API to help the SAT solver remember eliminated variablesClifford Wolf2014-03-014-3/+17
* ezSAT bugfix: don't call virtual methods in base class constructorClifford Wolf2014-03-012-2/+5
* Removed ezSAT::assumed() APIClifford Wolf2014-03-013-10/+0
* Removed ezSAT built-in brute-froce solverClifford Wolf2014-03-011-102/+6
* Fixed vhdl2verilog temp dir nameClifford Wolf2014-03-011-1/+1
* Fixed vhdl2verilog help messageClifford Wolf2014-03-011-3/+2
* Fixed const folding of $bu0 cellsClifford Wolf2014-02-272-1/+2