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* | Fixed more visual studio warningsClifford Wolf2016-02-141-5/+3
* | Fixed some visual studio warningsClifford Wolf2016-02-138-10/+10
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-02-131-1/+1
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| * | Fixed MXE ABC buildClifford Wolf2016-02-131-1/+1
* | | Added "int ceil_log2(int)" functionClifford Wolf2016-02-135-10/+58
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* | Run dffsr2dff in synth_xilinxClifford Wolf2016-02-131-0/+2
* | Support for more Verific primitives (patch I got per email)Clifford Wolf2016-02-131-1/+31
* | Updated ABCClifford Wolf2016-02-081-1/+1
* | Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-071-1/+7
* | Updated ABCClifford Wolf2016-02-071-1/+1
* | Added "stat -liberty" for calculating chip areaClifford Wolf2016-02-041-6/+60
* | Bugfix in Verific front-endClifford Wolf2016-02-031-2/+5
* | Updated verific build instructionsClifford Wolf2016-02-021-2/+0
* | Improved dffsr2dff passClifford Wolf2016-02-021-5/+50
* | Added dffsr2dffClifford Wolf2016-02-023-0/+171
* | Added addBufGate module methodClifford Wolf2016-02-023-0/+8
* | Use alphanumerical order instead of idstring idx in opt_clean compare_signals()Clifford Wolf2016-02-021-1/+1
* | Added CodeOfConductClifford Wolf2016-02-011-0/+73
* | Updated ABC to hg rev ee212a9e94dfClifford Wolf2016-02-011-1/+1
* | Progress in cell library documentationClifford Wolf2016-02-011-0/+238
* | Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-012-15/+39
* | Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)Clifford Wolf2016-02-011-8/+68
* | SigMap performance improvementClifford Wolf2016-02-011-1/+7
* | hashlib mfp<> performance improvementsClifford Wolf2016-02-011-2/+7
* | Added reserve() method to haslib classes andClifford Wolf2016-01-311-2/+6
* | Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosysClifford Wolf2016-01-312-14/+88
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| * | rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)Rick Altherr2016-01-311-2/+31
| * | rtlil: speed up SigSpec::sort_and_unify()Rick Altherr2016-01-311-1/+11
| * | rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)Rick Altherr2016-01-311-6/+14
| * | genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSi...Rick Altherr2016-01-311-3/+3
| * | rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)Rick Altherr2016-01-311-2/+29
* | | More clang sanitizer stuffClifford Wolf2016-01-312-3/+12
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* | Meaningless coding style changeClifford Wolf2016-01-311-1/+0
* | Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosysClifford Wolf2016-01-312-23/+37
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| * | rtlil: rewrite remove2() to avoid copyingRick Altherr2016-01-301-45/+18
| * | rtlil: duplicate remove2() for std::set<>Rick Altherr2016-01-292-0/+41
| * | rtlil: change IdString comparison operators to take references instead of copiesRick Altherr2016-01-291-3/+3
* | | Addedd clang sanitizersClifford Wolf2016-01-311-0/+21
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* | Added "equiv_struct -fwonly"Clifford Wolf2016-01-081-5/+17
* | Bugfixes in equiv_structClifford Wolf2016-01-081-2/+9
* | Added "submod -copy"Clifford Wolf2016-01-081-13/+28
* | Added "write_blif -cname" modeClifford Wolf2016-01-061-1/+12
* | Added "equiv_struct -maxiter <N>"Clifford Wolf2016-01-061-4/+16
* | Added "equiv_add -try" modeClifford Wolf2016-01-061-6/+33
* | Fixed "splitnets -ports" for hierarchical designsClifford Wolf2015-12-221-0/+57
* | Re-run ice40_opt in "synth_ice40 -abc2"Clifford Wolf2015-12-221-1/+4
* | Improvements in ice40_optClifford Wolf2015-12-221-5/+16
* | Bugfix in ice40_ffinitClifford Wolf2015-12-221-2/+2
* | Improved ice40_ffinitClifford Wolf2015-12-221-1/+22
* | Run opt_const before check in default scriptsClifford Wolf2015-12-222-0/+4
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