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* | | | | | Resolve struct member package typesDag Lem2023-01-292-0/+11
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* | | | | | Handle struct members of union type (#3641)Dag Lem2023-01-293-2/+18
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* | | | | Bump versiongithub-actions[bot]2023-01-261-1/+1
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* | | | | Merge pull request #3647 from jix/formalff-hierarchy-fixMiodrag Milanović2023-01-251-1/+1
|\ \ \ \ \ | | | | | | | | | | | | formalff: Fix crash with _NOT_ gates in -hierarchy mode
| * | | | | formalff: Fix crash with _NOT_ gates in -hierarchy modeJannis Harder2023-01-251-1/+1
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* | | | | Bump versiongithub-actions[bot]2023-01-241-1/+1
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* | | | | Merge pull request #3624 from jix/sim_ywMiodrag Milanović2023-01-2315-113/+1722
|\ \ \ \ \ | | | | | | | | | | | | Changes to support SBY trace generation with the sim command
| * | | | | sim/formalff: Clock handling for yw cosimJannis Harder2023-01-115-33/+274
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| * | | | | sim: Improvements and fixes for yw cosimJannis Harder2023-01-116-52/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Fixed $cover handling * Improved sparse memory handling when writing traces * JSON summary output
| * | | | | Support for BTOR witness to Yosys witness conversionJannis Harder2023-01-115-20/+312
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| * | | | | aiger: Use new JSON code for writing aiger witness map filesJannis Harder2023-01-113-55/+96
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| * | | | | Add json.{h,cc} for pretty printing JSONJannis Harder2023-01-113-1/+223
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoids errors in trailing comma handling, broken indentation and improper escaping that is common when building JSON by manually concatenating strings.
| * | | | | sim: New -append option for Yosys witness cosimJannis Harder2023-01-111-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | This is needed to support SBY's append option.
| * | | | | sim: Add Yosys witness (.yw) cosimulationJannis Harder2023-01-111-3/+194
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| * | | | | New kernel/yw.{h,cc} to support reading Yosys witness filesJannis Harder2023-01-113-1/+380
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This contains parsing code as well as generic routines to associate the hierarchical signals paths within a Yosys witness file to a loaded RTLIL design, including support for memories.
| * | | | | sim: Only check formal cells during gclk simulation updatesJannis Harder2023-01-111-16/+19
| | | | | | | | | | | | | | | | | | | | | | | | This is required for compatibility with non-multiclock formal semantics.
| * | | | | sim: Internal API to set $initstateJannis Harder2023-01-111-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | This is not yet added to any of the simulation drivers.
| * | | | | sim: Emit used memory addresses as signals to output tracesJannis Harder2023-01-111-17/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the behavior of smtbmc. This also updates the sim internal memory API to allow masked writes where State::Sa bits (internal don't care - not a valid value for a signal) leave the memory content unchanged.
| * | | | | xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundefJannis Harder2023-01-113-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the xprop_decoder attribute to bwmuxes that drive the original unencoded signals. Setundef is changed to ignore the x inputs of these bwmuxes, so that they survive the prep script of SBY's formal flow. This is required to make simulation (via sim) using the prep model show the decoded x signals instead of 0/1 values made up by the solver.
| * | | | | smt2: Treat bweqx as xnorJannis Harder2023-01-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Without x-bits they are equivalent
| * | | | | smt2: Directly implement bwmux instead of using bwmuxmapJannis Harder2023-01-111-2/+4
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* | | | | | Merge pull request #3629 from YosysHQ/micko/clang_fixesMiodrag Milanović2023-01-2315-23/+39
|\ \ \ \ \ \ | | | | | | | | | | | | | | Fixes for some of clang scan-build detected issues
| * | | | | | Fixes for some of clang scan-build detected issuesMiodrag Milanovic2023-01-1715-23/+39
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* | | | | | Merge pull request #3636 from YosysHQ/log_pluginMiodrag Milanović2023-01-231-0/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | Call yosys_shutdown to properly cleanup plugins and tcl when expecting error
| * | | | | | Call yosys_shutdown to properly cleanup plugins and tcl when expecting errorMiodrag Milanovic2023-01-201-0/+1
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* | | | | | | show: Remove left-in debug log_warninggatecat2023-01-231-1/+0
|/ / / / / / | | | | | | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | | | | Merge pull request #3630 from yrabbit/gw1n4c-pllMiodrag Milanović2023-01-181-0/+47
|\ \ \ \ \ \ | | | | | | | | | | | | | | gowin: add a new type of PLL - PLLVR
| * | | | | | gowin: add a new type of PLL - PLLVRYRabbit2023-01-111-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This primitive is used in the GW1NS-4, GW1NS-4C, GW1NSR-4, GW1NSR-4C and GW1NSER-4C chips. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | | | | | Bump versiongithub-actions[bot]2023-01-181-1/+1
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* | | | | | | Improve splitcells passClaire Xenia Wolf2023-01-181-52/+120
| |/ / / / / |/| | | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | | | Bump versiongithub-actions[bot]2023-01-121-1/+1
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* | | | | | print filename in liberty log_headerN. Engelhardt2023-01-111-2/+2
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* | | | | Merge pull request #3605 from gadfort/stat-json-areaN. Engelhardt2023-01-111-0/+3
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| * | | | Merge branch 'master' into stat-json-areaPeter Gadfort2023-01-0289-20297/+11
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| * | | | | stat: ensure area is included in json outputPeter Gadfort2022-12-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
* | | | | | Merge pull request #3570 from YosysHQ/claire/eqystuffClaire Xen2023-01-118-17/+1380
|\ \ \ \ \ \ | | | | | | | | | | | | | | Various Changes for EQY
| * \ \ \ \ \ Merge branch 'master' into claire/eqystuffClaire Xen2023-01-1112-131/+60
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* | | | | | | Merge pull request #3537 from jix/xpropJannis Harder2023-01-1129-79/+2537
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | New xprop pass
* | | | | | | | remove template declaration that stops function from being usedN. Engelhardt2023-01-111-4/+0
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* | | | | | | | Merge pull request #3620 from YosysHQ/gcc48_removeN. Engelhardt2023-01-1111-127/+60
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| * | | | | | | Add deprecation info to changelogMiodrag Milanovic2023-01-111-0/+2
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| * | | | | | | Deprecate gcc-4.8Miodrag Milanovic2023-01-1110-127/+58
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| | * | | | | Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuffClaire Xenia Wolf2023-01-11103-20236/+385
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* | | | | | | Bump versiongithub-actions[bot]2023-01-111-1/+1
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* | | | | | | Merge pull request #3616 from YosysHQ/register_errorMiodrag Milanović2023-01-101-5/+12
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Display error instead of assertion when pass exists
| * | | | | | | Display error instead of assertion when pass existsMiodrag Milanovic2023-01-091-5/+12
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* | | | | | | | Merge pull request #3615 from YosysHQ/qbfsat_cvc5Miodrag Milanović2023-01-102-3/+7
|\ \ \ \ \ \ \ \ | |/ / / / / / / |/| | | | | | | qbfsat support for cvc5, fixes #3608
| * | | | | | | qbfsat support for cvc5, fixes #3608Miodrag Milanovic2023-01-092-3/+7
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* | | | | | | Bump versiongithub-actions[bot]2023-01-051-1/+1
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* | | | | | | nexus: Fix BRAM write enable in PDP modegatecat2023-01-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>