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| * | | Missing equiv_opt -assertEddie Hung2019-09-061-1/+1
| * | | Make one check $shift(x)? only; change testcase to be 8bEddie Hung2019-09-062-4/+5
| * | | Usee equiv_opt -assertEddie Hung2019-09-061-3/+3
| * | | simple/peepopt.v tests to various/peepopt.ys with equiv_opt & selectEddie Hung2019-09-052-21/+63
| * | | Revert "abc9 followed by clean otherwise netlist could be invalid for sim"Eddie Hung2019-09-051-1/+0
| * | | Revert "parse_xaiger() to do "clean -purge""Eddie Hung2019-09-041-1/+1
| * | | abc9 followed by clean otherwise netlist could be invalid for simEddie Hung2019-09-041-0/+1
| * | | Remove log_cell() callsEddie Hung2019-09-041-3/+0
| * | | Add peepopt_dffmuxextEddie Hung2019-09-043-0/+60
| * | | Add peepopt_dffmuxext testsEddie Hung2019-09-041-0/+8
* | | | Merge pull request #1379 from mmicko/sim_modelsEddie Hung2019-09-182-7/+162
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| * | | | make note that it is for latch modeMiodrag Milanovic2019-09-181-0/+1
| * | | | better lut handlingMiodrag Milanovic2019-09-181-4/+14
| * | | | better handling of lut and begin/end addMiodrag Milanovic2019-09-181-4/+10
| * | | | Added simulation models for Efinix and AnlogicMiodrag Milanovic2019-09-152-3/+141
* | | | | Add "write_aiger -L"Clifford Wolf2019-09-181-5/+16
* | | | | Fix stupid bug in btor back-endClifford Wolf2019-09-181-1/+1
* | | | | Bump versionClifford Wolf2019-09-161-1/+1
* | | | | Merge pull request #1380 from YosysHQ/clifford/fix1372Clifford Wolf2019-09-161-2/+9
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| * | | | | Fix handling of range selects on loop variables, fixes #1372Clifford Wolf2019-09-161-2/+9
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* | | | | Merge pull request #1374 from YosysHQ/eddie/fix1371Eddie Hung2019-09-152-5/+25
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| * | | | | SpacingEddie Hung2019-09-131-1/+1
| * | | | | Explicitly order function argumentsEddie Hung2019-09-131-4/+15
| * | | | | Use template specialisationEddie Hung2019-09-131-2/+9
| * | | | | Revert "SigSet<Cell*> to use stable compare class"Eddie Hung2019-09-135-6/+6
| * | | | | GrammarEddie Hung2019-09-121-1/+1
| * | | | | static_assert to enforce this going forwardEddie Hung2019-09-121-0/+2
| * | | | | SigSet<Cell*> to use stable compare classEddie Hung2019-09-125-6/+6
* | | | | | xilinx: Make blackbox library family-dependent.Marcin Kościelnicki2019-09-157-1024/+19252
* | | | | | Merge pull request #1377 from YosysHQ/clifford/fixzdigitClifford Wolf2019-09-152-5/+5
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| * | | | | Fix handling of z_digit "?" and fix optimization of cmp with "z"Clifford Wolf2019-09-132-5/+5
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* | | | | Merge pull request #1373 from YosysHQ/clifford/fix1364Clifford Wolf2019-09-132-3/+3
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| * | | | Fix lexing of integer literals without radixClifford Wolf2019-09-131-1/+1
| * | | | Fix lexing of integer literals, fixes #1364Clifford Wolf2019-09-122-3/+3
* | | | | Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclockDavid Shah2019-09-122-1/+23
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| * | | | Add equiv_opt -multiclockDavid Shah2019-09-112-1/+23
* | | | | Add -match-init option to dff2dffs.Marcin Kościelnicki2019-09-113-3/+77
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* | | | Merge pull request #1362 from xobs/smtbmc-msvc2-build-fixesDavid Shah2019-09-114-9/+10
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| * | | | tests: ice40: fix div_mod SB_LUT4 countSean Cross2019-09-101-1/+1
| * | | | passes: opt_share: don't statically initialize mergeable_type_mapSean Cross2019-09-091-3/+4
| * | | | msys2: launcher: fix warnings and errors under g++Sean Cross2019-09-081-4/+4
| * | | | backends: smt2: use $(CXX) variable for compilerSean Cross2019-09-081-1/+1
* | | | | Bump versionClifford Wolf2019-09-101-1/+1
* | | | | Fix misspellingEddie Hung2019-09-091-1/+1
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* | | | synth_xilinx: Support init values on Spartan 6 flip-flops properly.Marcin Kościelnicki2019-09-075-53/+219
* | | | techmap: Add support for extracting init values of portsMarcin Kościelnicki2019-09-073-1/+169
* | | | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-09-0628-215/+719
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| * \ \ \ Merge pull request #1312 from YosysHQ/xaig_arrivalEddie Hung2019-09-0525-196/+657
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| | * | | | Resolve TODO with pin assignments for SRL*Eddie Hung2019-09-041-4/+2
| | * | | | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-09-046-5/+63
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