iCE40/yosys - [no description]

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* \| \|	Merge pull request #2272 from whitequark/write-verilog-sv	clairexen	2020-07-16	2	-11/+20
\|\\| \| \| \| \| \| \| \|	verilog_backend: add `-sv` option, make `-o <filename>.sv` work
\| * \|	verilog_backend: add `-sv` option, make `-o <filename>.sv` work.	whitequark	2020-07-16	2	-11/+20
\| \| \| \| \| \| \| \| \| \| \| \|	See #2271.
* \| \|	Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic	Miodrag Milanović	2020-07-16	4	-62/+49
\|\ \ \ \| \| \| \| \| \| \| \|	anlogic: Use dfflegalize.
\| * \| \|	anlogic: Use dfflegalize.	Marcelina Kościelnicka	2020-07-14	4	-62/+49
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* \| \| \|	Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbuf	Miodrag Milanović	2020-07-16	5	-122/+11
\|\ \ \ \ \| \| \| \| \| \| \| \| \| \|	efinix: Nuke efinix_gbuf in favor of clkbufmap.
\| * \| \| \|	efinix: Nuke efinix_gbuf in favor of clkbufmap.	Marcelina Kościelnicka	2020-07-04	5	-122/+11
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* \| \| \| \|	Merge pull request #2270 from whitequark/cxxrtl-fix-typo	whitequark	2020-07-16	1	-1/+1
\|\ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \|	cxxrtl: fix typo
\| * \| \| \| \|	cxxrtl: fix typo. NFC.	whitequark	2020-07-14	1	-1/+1
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* \| \| \| \|	Merge pull request #2269 from YosysHQ/claire/bisonwall	whitequark	2020-07-15	2	-64/+57
\|\ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \|	Use "bison -Wall -Werror" for verilog front-end
\| * \| \| \| \|	Treat all bison warnings as errors in verilog front-end	Claire Wolf	2020-07-15	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Claire Wolf <claire@symbioticeda.com>
\| * \| \| \| \|	Use %precedence in verilog_parser.y	Claire Wolf	2020-07-15	1	-4/+4
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Claire Wolf <claire@symbioticeda.com>
\| * \| \| \| \|	Fix bison warnings for missing %empty	Claire Wolf	2020-07-15	1	-59/+52
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Claire Wolf <claire@symbioticeda.com>
\| * \| \| \| \|	Run bison with -Wall for verilog front-end	Claire Wolf	2020-07-15	1	-1/+1
\|/ / / / / \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* \| \| \| \|	Merge pull request #2257 from antmicro/fix-conflicts	clairexen	2020-07-15	5	-9/+59
\|\ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \|	Restore #2203 and #2244 and fix parser conflicts
\| * \| \| \| \|	Add missing semicolons	Kamil Rakoczy	2020-07-15	1	-5/+5
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
\| * \| \| \| \|	Fix S/R conflicts	Kamil Rakoczy	2020-07-10	1	-1/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This commit fixes S/R conflicts introduced by commit 6f9be93. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
\| * \| \| \| \|	Fix R/R conflicts	Kamil Rakoczy	2020-07-10	1	-10/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This commit fixes R/R conflicts introduced by commit 7e83a51. Parameter logic is already defined as part of `param_range_type` rule. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
\| * \| \| \| \|	Revert "Revert PRs #2203 and #2244."	Kamil Rakoczy	2020-07-10	5	-10/+68
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
* \| \| \| \| \|	opt_merge: Dedup one more use of FF cell type list.	Marcelina Kościelnicka	2020-07-15	1	-3/+1
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* \| \| \| \| \|	achronix: Use dfflegalize.	Marcelina Kościelnicka	2020-07-14	1	-1/+1
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* \| \| \| \|	intel: Use dfflegalize.	Marcelina Kościelnicka	2020-07-13	8	-178/+17
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* \| \| \| \|	Revert "intel_alm: direct M10K instantiation"	Lofty	2020-07-13	8	-128/+38
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* \| \| \| \|	Merge pull request #2263 from whitequark/cxxrtl-capi-eval-commit	whitequark	2020-07-13	2	-0/+20
\|\ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \|	cxxrtl: expose eval() and commit() via the C API
\| * \| \| \| \|	cxxrtl: expose eval() and commit() via the C API.	whitequark	2020-07-12	2	-0/+20
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* \| \| \| \|	xilinx: Fix srl regression.	Marcelina Kościelnicka	2020-07-12	2	-2/+43
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* \| \| \| \|	proc_dlatch: Remove init values for combinatorial processes.	Marcelina Kościelnicka	2020-07-12	1	-0/+33
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fixes #2258.
* \| \| \| \|	dfflegalize: Gather init values from all wires.	Marcelina Kościelnicka	2020-07-12	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Skipping non-selected wires is unsound in an obvious way.
* \| \| \| \|	Merge pull request #2256 from YosysHQ/claire/fix2241	clairexen	2020-07-10	1	-0/+2
\|\ \ \ \ \ \| \|/ / / / \|/\| \| \| \|	Add AST_EDGE support to AstNode::detect_latch()
\| * \| \| \|	Add AST_EDGE support to AstNode::detect_latch(), fixes #2241	Claire Wolf	2020-07-10	1	-0/+2
\|/ / / / \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* \| \| \|	Merge pull request #2255 from whitequark/bison-Werror-conflicts	whitequark	2020-07-09	6	-69/+11
\|\ \ \ \ \| \| \| \| \| \| \| \| \| \|	verilog_parser: turn S/R and R/R conflicts into hard errors
\| * \| \| \|	verilog_parser: turn S/R and R/R conflicts into hard errors.	whitequark	2020-07-09	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fixes #2253.
\| * \| \| \|	Revert PRs #2203 and #2244.	whitequark	2020-07-09	5	-68/+10
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15. This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405. This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3. This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68. This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
* \| \| \| \|	Merge pull request #2254 from whitequark/cxxrtl-extern-c	whitequark	2020-07-09	1	-0/+1
\|\ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \|	cxxrtl: add missing extern "C"
\| * \| \| \| \|	cxxrtl: add missing extern "C".	whitequark	2020-07-09	1	-0/+1
\| \|/ / / / \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This bug was hidden if a header was generated.
* / / / /	sf2: Use dfflegalize.	Marcelina Kościelnicka	2020-07-09	2	-44/+13
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* \| \| \|	xilinx: Use dfflegalize.	Marcelina Kościelnicka	2020-07-09	6	-484/+131
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* \| \| \|	dfflibmap: Refactor to use dfflegalize internally.	Marcelina Kościelnicka	2020-07-09	5	-212/+214
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* \| \| \|	Fix issue #2251 (#2252)	Lucas Castro	2020-07-09	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* Fix #2251 - YosysJS ReferenceError: _memset is not defined. Add '_memset' in emcc EXPORTED_FUNCTIONS in Makefile.
* \| \| \|	clkbufmap: improve input pad handling.	Marcelina Kościelnicka	2020-07-09	2	-17/+118
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	- allow inserting only the input pad cell - do not insert the usual buffer if the input pad already acts as a buffer
* \| \| \|	Merge pull request #2244 from antmicro/logic	clairexen	2020-07-09	4	-7/+31
\|\ \ \ \ \| \| \| \| \| \| \| \| \| \|	Add logic type support to parameters
\| * \| \| \|	Add logic param and integer bad syntax tests	Kamil Rakoczy	2020-07-06	3	-0/+21
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
\| * \| \| \|	Support logic typed parameters	Lukasz Dalek	2020-07-06	1	-7/+10
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* \| \| \| \|	clk2fflogic: Consistently treat async control signals as negative hold.	Marcelina Kościelnicka	2020-07-09	8	-88/+82
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This fixes some dfflegalize equivalence checks, and breaks others — and I strongly suspect the others are due to bad support for multiple async inputs in `proc` (in particular, lack of proper support for dlatchsr and sketchy circuits on dffsr control inputs).
* \| \| \| \|	dfflegalize: Add special support for const-D latches.	Marcelina Kościelnicka	2020-07-09	2	-0/+71
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Those can be created by `opt_dff` when optimizing `$adff` with const clock, or with D == Q. Make dfflegalize do the opposite transform when such dlatches would be otherwise unimplementable.
* \| \| \| \|	Merge pull request #2246 from YosysHQ/mwk/dfflegalize-typo	whitequark	2020-07-07	1	-1/+1
\|\ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \|	dfflegalize: typo fix
\| * \| \| \| \|	dfflegalize: typo fix	Marcelina Kościelnicka	2020-07-07	1	-1/+1
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* \| \| \| \|	efinix: Use dfflegalize.	Marcelina Kościelnicka	2020-07-06	2	-15/+53
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* \| \| \| \|	gowin: Use dfflegalize.	Marcelina Kościelnicka	2020-07-06	4	-158/+49
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* \| \| \|	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-05	8	-38/+128
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* \| \| \|	Naming fixes.	Marcelina Kościelnicka	2020-07-05	2	-2/+2
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