| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | | * | | | | | | Merge pull request #1239 from mmicko/mingw_fix | Clifford Wolf | 2019-08-02 | 11 | -25/+37 | |
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| | | | * | | | | | | Fix linking issue for new mxe and pthread | Miodrag Milanovic | 2019-08-01 | 1 | -1/+2 | |
| | | | * | | | | | | Fix yosys linking for mxe | Miodrag Milanovic | 2019-08-01 | 1 | -1/+1 | |
| | | | * | | | | | | New mxe hacks needed to support 2ca237e | Miodrag Milanovic | 2019-08-01 | 1 | -0/+4 | |
| | | | * | | | | | | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-01 | 10 | -23/+30 | |
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| | * | | | | | | | Do not pack registers if (* keep *) | Eddie Hung | 2019-08-07 | 1 | -0/+20 | |
| * | | | | | | | | DSP48E1 sim model: add SIMD tests | David Shah | 2019-08-08 | 3 | -3/+113 | |
| * | | | | | | | | DSP48E1 model: test CE inputs | David Shah | 2019-08-08 | 2 | -7/+17 | |
| * | | | | | | | | DSP48E1 sim model: fix seq tests and add preadder tests | David Shah | 2019-08-08 | 2 | -6/+91 | |
| * | | | | | | | | DSP48E1 sim model: seq test working | David Shah | 2019-08-08 | 3 | -16/+60 | |
| * | | | | | | | | DSP48E1 sim model: Comb, no pre-adder, mode working | David Shah | 2019-08-08 | 2 | -8/+13 | |
| * | | | | | | | | [wip] sim model testing | David Shah | 2019-08-08 | 4 | -15/+77 | |
| * | | | | | | | | [wip] sim model testing | David Shah | 2019-08-08 | 3 | -40/+360 | |
| * | | | | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-07 | 1 | -6/+82 | |
| * | | | | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -23/+120 | |
| * | | | | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -8/+75 | |
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| * | | | | | | | Add comment about supporting $dffe in ice40_dsp | Eddie Hung | 2019-08-01 | 1 | -0/+1 | |
| * | | | | | | | Pack P register properly | Eddie Hung | 2019-08-01 | 1 | -2/+4 | |
| * | | | | | | | Trim Y_WIDTH | Eddie Hung | 2019-08-01 | 1 | -5/+3 | |
| * | | | | | | | Add DSP_SIGNEDONLY back | Eddie Hung | 2019-08-01 | 1 | -0/+16 | |
| * | | | | | | | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH | Eddie Hung | 2019-08-01 | 2 | -5/+12 | |
| * | | | | | | | Change $__softmul back to $mul | Eddie Hung | 2019-08-01 | 1 | -0/+1 | |
| * | | | | | | | Cope with sign extension in mul2dsp | Eddie Hung | 2019-08-01 | 2 | -14/+14 | |
| * | | | | | | | Revert "Do not do sign extension in techmap; let packer do it" | Eddie Hung | 2019-08-01 | 1 | -5/+14 | |
| * | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-01 | 25 | -86/+219 | |
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| | * | | | | | | Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map | Eddie Hung | 2019-08-01 | 1 | -3/+3 | |
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| | | * | | | | | RST -> RSTBRST for RAMB8BWER | Eddie Hung | 2019-07-29 | 1 | -3/+3 | |
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| | * | | | | | Merge pull request #1233 from YosysHQ/clifford/defer | Clifford Wolf | 2019-07-31 | 2 | -49/+21 | |
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| | | * | | | | Update README to use "read" instead of "read_verilog" | Clifford Wolf | 2019-07-29 | 1 | -48/+19 | |
| | | * | | | | Call "read_verilog" with -defer from "read" | Clifford Wolf | 2019-07-29 | 1 | -1/+2 | |
| | * | | | | | Merge pull request #1228 from YosysHQ/dave/yy_buf_size | Eddie Hung | 2019-07-29 | 1 | -0/+3 | |
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| | | * | | | | | verilog_lexer: Increase YY_BUF_SIZE to 65536 | David Shah | 2019-07-26 | 1 | -0/+3 | |
| | * | | | | | | Merge pull request #1234 from mmicko/fix_gzip_no_exist | David Shah | 2019-07-29 | 1 | -19/+21 | |
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| | | * | | | | | Fix case when file does not exist | Miodrag Milanovic | 2019-07-29 | 1 | -19/+21 | |
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| | * | | | | | Merge pull request #1226 from YosysHQ/dave/gzip | David Shah | 2019-07-27 | 8 | -13/+70 | |
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| | | * | | | | Update CHANGELOG | David Shah | 2019-07-26 | 1 | -1/+1 | |
| | | * | | | | Fix frontend auto-detection for gzipped input | David Shah | 2019-07-26 | 1 | -9/+12 | |
| | | * | | | | Add support for reading gzip'd input files | David Shah | 2019-07-26 | 6 | -3/+57 | |
| | * | | | | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-07-25 | 17 | -29/+360 | |
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| | | * \ \ \ \ | Merge branch 'ZirconiumX-synth_intel_m9k' | Clifford Wolf | 2019-07-25 | 4 | -5/+11 | |
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| | | | * | | | | | intel: Map M9K BRAM only on families that have it | Dan Ravensloft | 2019-07-23 | 4 | -5/+12 | |
| | | * | | | | | | Merge pull request #1218 from ZirconiumX/synth_intel_iopads | Clifford Wolf | 2019-07-25 | 1 | -8/+8 | |
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| | | | * | | | | | | intel: Make -noiopads the default | Dan Ravensloft | 2019-07-24 | 1 | -8/+8 | |
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| | | * | | | | | | Merge pull request #1219 from jakobwenzel/objIterator | Clifford Wolf | 2019-07-25 | 2 | -3/+20 | |
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| | | | * | | | | | | replaced std::iterator with using statements | Jakob Wenzel | 2019-07-25 | 1 | -6/+6 | |
| | | | * | | | | | | made ObjectIterator extend std::iterator | Jakob Wenzel | 2019-07-24 | 2 | -2/+19 | |
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| | | * | | | | | | Merge pull request #1224 from YosysHQ/xilinx_fix_ff | Eddie Hung | 2019-07-25 | 1 | -2/+2 | |
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| | | | * | | | | | xilinx: Fix missing cell name underscore in cells_map.v | David Shah | 2019-07-25 | 1 | -2/+2 | |
| | | * | | | | | | Merge pull request #1222 from koriakin/s6-example | Eddie Hung | 2019-07-24 | 5 | -0/+47 | |
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| | | | * | | | | | Add a simple example for Spartan 6 | Marcin Kościelnicki | 2019-07-24 | 5 | -0/+47 | |
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index : iCE40/yosys | |
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