| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | | | | Use single DSP_SIGNEDONLY macro | Eddie Hung | 2019-07-18 | 1 | -1/+1 | |
| * | | | | | | Working for unsigned | Eddie Hung | 2019-07-18 | 1 | -52/+28 | |
| * | | | | | | Cleanup | Eddie Hung | 2019-07-18 | 1 | -70/+58 | |
| * | | | | | | Wrong wildcard symbol | Eddie Hung | 2019-07-18 | 1 | -1/+1 | |
| * | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-18 | 1 | -31/+41 | |
| |\ \ \ \ \ \ | ||||||
| | * | | | | | | mul2dsp: Lower partial products always have unsigned inputs | David Shah | 2019-07-18 | 1 | -31/+41 | |
| * | | | | | | | Make all operands signed | Eddie Hung | 2019-07-17 | 1 | -1/+1 | |
| * | | | | | | | Update comment | Eddie Hung | 2019-07-17 | 1 | -5/+3 | |
| |/ / / / / / | ||||||
| * | | | | | | Pattern matcher to check pool of bits, not exactly | Eddie Hung | 2019-07-17 | 2 | -5/+11 | |
| * | | | | | | Fix mul2dsp signedness | Eddie Hung | 2019-07-17 | 1 | -42/+38 | |
| * | | | | | | A_SIGNED == B_SIGNED so flip both | Eddie Hung | 2019-07-17 | 1 | -21/+12 | |
| * | | | | | | SigSpec::remove_const() to return SigSpec& | Eddie Hung | 2019-07-17 | 2 | -2/+3 | |
| * | | | | | | Add DSP_{A,B}_SIGNEDONLY macro | Eddie Hung | 2019-07-16 | 1 | -11/+40 | |
| * | | | | | | Signedness | Eddie Hung | 2019-07-16 | 2 | -8/+8 | |
| * | | | | | | Signed extension | Eddie Hung | 2019-07-16 | 2 | -6/+6 | |
| * | | | | | | Revert drop down to 24x16 multipliers for all | Eddie Hung | 2019-07-16 | 2 | -4/+4 | |
| * | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 4 | -27/+35 | |
| |\ \ \ \ \ \ | ||||||
| | * | | | | | | xilinx: Add correct signed behaviour to DSP48E1 model | David Shah | 2019-07-16 | 1 | -1/+1 | |
| | * | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 si... | David Shah | 2019-07-16 | 2 | -4/+8 | |
| | * | | | | | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH | David Shah | 2019-07-16 | 1 | -18/+22 | |
| | * | | | | | | mul2dsp: Fix indentation | David Shah | 2019-07-16 | 1 | -7/+7 | |
| * | | | | | | | Add support {A,B,P}REG packing | Eddie Hung | 2019-07-16 | 2 | -55/+94 | |
| * | | | | | | | SigSpec::extract to allow negative length | Eddie Hung | 2019-07-16 | 1 | -1/+1 | |
| * | | | | | | | Add support for {A,B,P}REG in DSP48E1 | Eddie Hung | 2019-07-16 | 1 | -5/+21 | |
| * | | | | | | | Do not swap if equals | Eddie Hung | 2019-07-15 | 1 | -1/+1 | |
| * | | | | | | | SigSpec::extend_u0() to return *this | Eddie Hung | 2019-07-15 | 2 | -2/+3 | |
| * | | | | | | | Oops forgot these files | Eddie Hung | 2019-07-15 | 3 | -2/+12 | |
| * | | | | | | | Add xilinx_dsp for register packing | Eddie Hung | 2019-07-15 | 3 | -2/+192 | |
| * | | | | | | | OUT port to Y in generic DSP | Eddie Hung | 2019-07-15 | 2 | -3/+3 | |
| * | | | | | | | Move DSP mapping back out to dsp_map.v | Eddie Hung | 2019-07-15 | 2 | -41/+40 | |
| |/ / / / / / | ||||||
| * | | | | | | Only swap if B_WIDTH > A_WIDTH | Eddie Hung | 2019-07-15 | 1 | -1/+1 | |
| * | | | | | | Tidy up | Eddie Hung | 2019-07-15 | 1 | -39/+26 | |
| * | | | | | | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim | Eddie Hung | 2019-07-15 | 2 | -82/+131 | |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-15 | 16 | -30/+639 | |
| |\| | | | | | ||||||
| | * | | | | | Merge pull request #1194 from cr1901/miss-semi | Eddie Hung | 2019-07-14 | 1 | -2/+2 | |
| | |\ \ \ \ \ | | |/ / / / | |/| | | | | ||||||
| | | * | | | | Fix missing semicolon in Windows-specific code in aigerparse.cc. | William D. Jones | 2019-07-14 | 1 | -2/+2 | |
| | * | | | | | Merge pull request #1183 from whitequark/ice40-always-relut | Clifford Wolf | 2019-07-12 | 1 | -11/+5 | |
| | |\ \ \ \ \ | | |_|_|/ / | |/| | | | | ||||||
| | | * | | | | synth_ice40: switch -relut to be always on. | whitequark | 2019-07-11 | 1 | -10/+4 | |
| | | * | | | | synth_ice40: fix help text typo. NFC. | whitequark | 2019-07-11 | 1 | -1/+1 | |
| | | |/ / / | ||||||
| | * | | | | Merge pull request #1182 from koriakin/xc6s-bram | Eddie Hung | 2019-07-11 | 9 | -8/+598 | |
| | |\ \ \ \ | ||||||
| | | * | | | | synth_xilinx: Initial Spartan 6 block RAM inference support. | Marcin Kościelnicki | 2019-07-11 | 9 | -8/+598 | |
| | | |/ / / | ||||||
| | * | | | | Merge pull request #1185 from koriakin/xc-ff-init-vals | Eddie Hung | 2019-07-11 | 2 | -6/+6 | |
| | |\ \ \ \ | ||||||
| | | * | | | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv... | Marcin Kościelnicki | 2019-07-11 | 2 | -6/+6 | |
| | | |/ / / | ||||||
| | * / / / | Enable &mfs for abc9, even if it only currently works for ice40 | Eddie Hung | 2019-07-11 | 1 | -1/+1 | |
| | |/ / / | ||||||
| | * | | | Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark | Clifford Wolf | 2019-07-11 | 1 | -2/+8 | |
| | |\ \ \ | ||||||
| | | * | | | write_verilog: write RTLIL::Sa aka - as Verilog ?. | whitequark | 2019-07-09 | 1 | -2/+8 | |
| | * | | | | Merge pull request #1179 from whitequark/attrmap-proc | Clifford Wolf | 2019-07-11 | 1 | -0/+19 | |
| | |\ \ \ \ | ||||||
| | | * | | | | attrmap: also consider process, switch and case attributes. | whitequark | 2019-07-10 | 1 | -0/+19 | |
| | | | |/ / | | |/| | | ||||||
| * | | | | | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little | Eddie Hung | 2019-07-10 | 4 | -45/+42 | |
| * | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-10 | 34 | -271/+734 | |
| |\| | | | | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |