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Age
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Rework help_mode for synth_xilinx -widemux
Eddie Hung
2019-06-26
1
-22
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+23
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Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
Eddie Hung
2019-06-26
1
-12
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+11
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Emprically (even if I don't fully understand it) this passes picorv32 tb
Eddie Hung
2019-06-26
1
-12
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+11
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Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
Eddie Hung
2019-06-26
1
-1
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+1
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Remove redundant check (done further down)
Eddie Hung
2019-06-26
1
-1
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+1
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Return to upstream synth_xilinx with opt -full and wreduce
Eddie Hung
2019-06-26
1
-19
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+3
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Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
Eddie Hung
2019-06-26
1
-1
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+1
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Restore sigmap wrapper
Eddie Hung
2019-06-26
1
-1
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+1
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Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
Eddie Hung
2019-06-26
2
-55
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+210
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Add more tests
Eddie Hung
2019-06-26
1
-0
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+152
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muxcover to be undef-sensitive when computing decoders
Eddie Hung
2019-06-26
1
-21
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+40
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Revert "Rework muxcover decoder gen if more significant muxes are 1'bx"
Eddie Hung
2019-06-26
1
-55
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+39
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Let's not go crazy: use nonzero costs
Eddie Hung
2019-06-26
1
-6
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+6
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Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
Eddie Hung
2019-06-26
9
-91
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+350
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Rework muxcover decoder gen if more significant muxes are 1'bx
Eddie Hung
2019-06-26
1
-39
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+55
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Add tests
Eddie Hung
2019-06-26
1
-0
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+168
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Merge pull request #1137 from mmicko/cell_sim_fix
Clifford Wolf
2019-06-26
2
-14
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+1
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Simulation model verilog fix
Miodrag Milanovic
2019-06-26
2
-14
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+1
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Improve opt_clean handling of unused public wires
Clifford Wolf
2019-06-26
1
-2
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+2
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Improve BTOR2 handling of undriven wires
Clifford Wolf
2019-06-26
1
-3
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+27
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Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131
Clifford Wolf
2019-06-26
1
-1
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+1
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Do not clean up buffer cells with "keep" attribute, closes #1128
Clifford Wolf
2019-06-26
1
-1
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+1
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Escape scope names starting with dollar sign in smtio.py
Clifford Wolf
2019-06-26
1
-1
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+4
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Add more ECP5 Diamond flip-flops.
whitequark
2019-06-26
2
-30
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+91
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Instead of blocking wreduce on $mux, use -keepdc instead #1132
Eddie Hung
2019-06-26
1
-2
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+2
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Do not call opt with -full before muxcover
Eddie Hung
2019-06-26
1
-1
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+1
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-26
1
-1
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+1
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Remove unused var
Eddie Hung
2019-06-26
1
-1
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+1
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Cleanup abc_box_id
Eddie Hung
2019-06-26
2
-10
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+10
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-26
4
-19
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+67
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Add _nowide variants of LUT libraries in -nowidelut flows
Eddie Hung
2019-06-26
4
-13
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+44
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung
2019-06-26
1
-2
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+10
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Merge branch 'koriakin/xc7nocarrymux' into xaig
Eddie Hung
2019-06-26
0
-0
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+0
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Fix spacing
Eddie Hung
2019-06-26
1
-5
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+5
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Merge branch 'koriakin/xc7nocarrymux' into xaig
Eddie Hung
2019-06-26
0
-0
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+0
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Oops. Actually use nocarry flag as spotted by @koriakin
Eddie Hung
2019-06-26
1
-5
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+7
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Merge branch 'koriakin/xc7nocarrymux' into xaig
Eddie Hung
2019-06-26
2
-9
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+26
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synth_ecp5 rename -nomux to -nowidelut, but preserve former
Eddie Hung
2019-06-26
1
-6
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+6
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Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriak...
Eddie Hung
2019-06-26
1
-4
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+24
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synth_xilinx: Add -nocarry and -nomux options.
Marcin Kościelnicki
2019-04-30
1
-7
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+26
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Rename -minmuxf to -widemux
Eddie Hung
2019-06-26
1
-23
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+23
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-26
1
-2
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+10
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Merge pull request #1136 from YosysHQ/xaig_ice40_wire_del
Eddie Hung
2019-06-26
1
-2
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+10
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abc9: Add wire delays to synth_ice40
David Shah
2019-06-26
1
-2
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+10
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-25
0
-0
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+0
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Missing muxpack.o in Makefile
Eddie Hung
2019-06-25
1
-0
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+1
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-25
7
-35
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+235
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Realistic delays for RAM32X1D too
Eddie Hung
2019-06-25
1
-2
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+2
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Add RAM32X1D box info
Eddie Hung
2019-06-25
2
-4
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+12
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-25
13
-14
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+1029
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