| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | Add Verific SVA support for "always" properties | Clifford Wolf | 2019-11-22 | 1 | -5/+15 | |
| | |/ / / / / | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | Merge pull request #1511 from YosysHQ/dave/always | Clifford Wolf | 2019-11-22 | 6 | -9/+126 | |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | sv: Error checking for always_comb, always_latch and always_ff | |||||
| | | * | | | | | Update CHANGELOG and README | David Shah | 2019-11-22 | 2 | -0/+7 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | sv: Add tests for SV always types | David Shah | 2019-11-21 | 1 | -0/+63 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage | David Shah | 2019-11-21 | 1 | -4/+16 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | sv: Correct parsing of always_comb, always_ff and always_latch | David Shah | 2019-11-21 | 2 | -5/+40 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | | | | gowin: Remove show command from tests. | Marcin Kościelnicki | 2019-11-22 | 1 | -1/+0 | |
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| | * | | | | | | gowin: Add missing .gitignore entries | Marcin Kościelnicki | 2019-11-22 | 1 | -0/+2 | |
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| | * | | | | | Merge pull request #1507 from YosysHQ/clifford/verificfixes | Clifford Wolf | 2019-11-20 | 2 | -6/+9 | |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | Some fixes in our Verific integration | |||||
| | | * | | | | | Correctly treat empty modules as blackboxes in Verific | Clifford Wolf | 2019-11-20 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | Do not rename VHDL entities to "entity(impl)" when they are top modules | Clifford Wolf | 2019-11-20 | 2 | -5/+8 | |
| | |/ / / / / | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | Revert "write_xaiger to not use module POs but only write outputs if driven" | Eddie Hung | 2019-11-22 | 1 | -23/+11 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 0ab1e496dc601f8e9d5efbcc5b2be7cf6b2d9673. | |||||
| * | | | | | | Missing endmodule | Eddie Hung | 2019-11-22 | 1 | -0/+1 | |
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| * | | | | | | write_xaiger to not use module POs but only write outputs if driven | Eddie Hung | 2019-11-21 | 1 | -11/+23 | |
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| * | | | | | | When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_ | Eddie Hung | 2019-11-21 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Since they should be captured downwards from the owning flop | |||||
| * | | | | | | Merge branch 'eddie/xaig_dff_adff' into xaig_dff | Eddie Hung | 2019-11-21 | 5 | -16/+55 | |
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| | * | | | | | Add a equiv test too | Eddie Hung | 2019-11-19 | 2 | -0/+23 | |
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| | * | | | | | Add two tests | Eddie Hung | 2019-11-19 | 1 | -0/+12 | |
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| | * | | | | | abc9 to support async flops $_DFF_[NP][NP][01]_ | Eddie Hung | 2019-11-19 | 1 | -1/+2 | |
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| | * | | | | | Do not drop async control signals in abc_map.v | Eddie Hung | 2019-11-19 | 1 | -12/+16 | |
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| * | | | | | | Add test | Eddie Hung | 2019-11-21 | 1 | -1/+6 | |
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| * | | | | | Consistent log message, ignore 's' extension | Eddie Hung | 2019-11-20 | 1 | -2/+3 | |
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| * | | | | | endomain -> ctrldomain | Eddie Hung | 2019-11-20 | 1 | -3/+3 | |
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| * | | | | | Add blackbox model for $__ABC9_FF_ so that clock partitioning works | Eddie Hung | 2019-11-20 | 1 | -0/+3 | |
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| * | | | | | Add multi clock test | Eddie Hung | 2019-11-20 | 1 | -0/+5 | |
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| * | | | | | Fix INIT values | Eddie Hung | 2019-11-20 | 1 | -4/+4 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 228 | -24028/+35109 | |
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| | * | | | Merge pull request #1449 from pepijndevos/gowin | Clifford Wolf | 2019-11-19 | 27 | -89/+841 | |
| | |\ \ \ | | | | | | | | | | | Improvements for gowin support | |||||
| | | * | | | Remove dff init altogether | Pepijn de Vos | 2019-11-19 | 2 | -3/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | The hardware does not actually support it. In reality it is always initialised to its reset value. | |||||
| | | * | | | add help for nowidelut and abc9 options | Pepijn de Vos | 2019-11-18 | 1 | -1/+7 | |
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| | | * | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-16 | 15 | -47/+913 | |
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| | | * | | | | fix fsm test with proper clock enable polarity | Pepijn de Vos | 2019-11-11 | 2 | -4/+15 | |
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| | | * | | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-11 | 29 | -23010/+30701 | |
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| | | * | | | | | fix wide luts | Pepijn de Vos | 2019-11-06 | 2 | -19/+22 | |
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| | | * | | | | | don't cound exact luts in big muxes; futile and fragile | Pepijn de Vos | 2019-10-30 | 1 | -3/+0 | |
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| | | * | | | | | add IOBUF | Pepijn de Vos | 2019-10-28 | 2 | -1/+10 | |
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| | | * | | | | | add tristate buffer and test | Pepijn de Vos | 2019-10-28 | 3 | -2/+21 | |
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| | | * | | | | | do not use wide luts in testcase | Pepijn de Vos | 2019-10-28 | 1 | -3/+3 | |
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| | | * | | | | | actually run the gowin tests | Pepijn de Vos | 2019-10-28 | 1 | -0/+1 | |
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| | | * | | | | | More formatting | Pepijn de Vos | 2019-10-28 | 1 | -55/+49 | |
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| | | * | | | | | really really fix formatting maybe | Pepijn de Vos | 2019-10-28 | 1 | -41/+41 | |
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| | | * | | | | | undo formatting fuckup | Pepijn de Vos | 2019-10-28 | 1 | -25/+25 | |
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| | | * | | | | | add wide luts | Pepijn de Vos | 2019-10-28 | 3 | -36/+119 | |
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| | | * | | | | | add 32-bit BRAM and byte-enables | Pepijn de Vos | 2019-10-28 | 2 | -4/+25 | |
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| | | * | | | | | ALU sim tweaks | Pepijn de Vos | 2019-10-24 | 2 | -13/+13 | |
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| | | * | | | | | Add some tests | Pepijn de Vos | 2019-10-21 | 10 | -0/+224 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram | |||||
| | | * | | | | | add a few more missing dff | Pepijn de Vos | 2019-10-21 | 1 | -7/+16 | |
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| | | * | | | | | add negedge DFF | Pepijn de Vos | 2019-10-21 | 2 | -15/+139 | |
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| | | * | | | | | use ADDSUB ALU mode to remove inverters | Pepijn de Vos | 2019-10-21 | 2 | -7/+77 | |
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| | | * | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-10-21 | 275 | -2678/+32872 | |
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index : iCE40/yosys | |
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