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* Merge pull request #1253 from YosysHQ/clifford/checkClifford Wolf2019-08-073-9/+17
|\ | | | | Be less aggressive with running design->check()
| * Be less aggressive with running design->check()Clifford Wolf2019-08-063-9/+17
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1257 from YosysHQ/clifford/cellcostsClifford Wolf2019-08-073-109/+103
|\ \ | | | | | | Redesign of cell cost API
| * | Tweak default gate costs, cleanup "stat -tech cmos"Clifford Wolf2019-08-072-20/+10
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Redesign of cell cost APIClifford Wolf2019-08-072-93/+97
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Update CHANGELOGDavid Shah2019-08-071-0/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #1241 from YosysHQ/clifford/jsonfixDavid Shah2019-08-072-36/+71
|\ \ \ | |/ / |/| | Improved JSON attr/param encoding
| * | Update JSON front-end to process new attr/param encodingClifford Wolf2019-08-011-23/+34
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Implement improved JSON attr/param encodingClifford Wolf2019-08-011-13/+37
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #1232 from YosysHQ/dave/write_gzipDavid Shah2019-08-064-7/+79
|\ \ \ | |_|/ |/| | Add support for writing gzip-compressed files
| * | Add test for writing gzip-compressed filesDavid Shah2019-08-062-0/+18
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | Add support for writing gzip-compressed filesDavid Shah2019-08-062-7/+61
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1251 from YosysHQ/clifford/nmuxClifford Wolf2019-08-0619-42/+174
|\ \ | | | | | | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
| * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-0619-42/+174
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1242 from jfng/fix-proc_prune-partialwhitequark2019-08-031-2/+11
|\ \ | | | | | | proc_prune: Promote partially redundant assignments.
| * | proc_prune: Promote partially redundant assignments.Jean-François Nguyen2019-08-011-2/+11
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* | Merge pull request #1238 from mmicko/vsbuild_fixClifford Wolf2019-08-022-1/+2
|\ \ | | | | | | Visual Studio build fix
| * | Visual Studio build fixMiodrag Milanovic2019-07-312-1/+2
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* | | Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-0211-25/+37
|\ \ \ | | | | | | | | Fix formatting for msys2 mingw build
| * | | Fix linking issue for new mxe and pthreadMiodrag Milanovic2019-08-011-1/+2
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| * | | Fix yosys linking for mxeMiodrag Milanovic2019-08-011-1/+1
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| * | | New mxe hacks needed to support 2ca237eMiodrag Milanovic2019-08-011-0/+4
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| * | | Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-0110-23/+30
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* | | Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_mapEddie Hung2019-08-011-3/+3
|\ \ \ | |_|/ |/| | xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER
| * | RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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* | Merge pull request #1233 from YosysHQ/clifford/deferClifford Wolf2019-07-312-49/+21
|\ \ | |/ |/| Call "read_verilog" with -defer from "read"
| * Update README to use "read" instead of "read_verilog"Clifford Wolf2019-07-291-48/+19
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Call "read_verilog" with -defer from "read"Clifford Wolf2019-07-291-1/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1228 from YosysHQ/dave/yy_buf_sizeEddie Hung2019-07-291-0/+3
|\ \ | | | | | | verilog_lexer: Increase YY_BUF_SIZE to 65536
| * | verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #1234 from mmicko/fix_gzip_no_existDavid Shah2019-07-291-19/+21
|\ \ \ | |_|/ |/| | Fix case when file does not exist
| * | Fix case when file does not existMiodrag Milanovic2019-07-291-19/+21
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* | Merge pull request #1226 from YosysHQ/dave/gzipDavid Shah2019-07-278-13/+70
|\ \ | |/ |/| Add support for gzip'd input files
| * Update CHANGELOGDavid Shah2019-07-261-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * Fix frontend auto-detection for gzipped inputDavid Shah2019-07-261-9/+12
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * Add support for reading gzip'd input filesDavid Shah2019-07-266-3/+57
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-07-2517-29/+360
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| * \ Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| | * | intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
| * | | Merge pull request #1218 from ZirconiumX/synth_intel_iopadsClifford Wolf2019-07-251-8/+8
| |\ \ \ | | | | | | | | | | intel: Make -noiopads the default
| | * | | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
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| * | | | Merge pull request #1219 from jakobwenzel/objIteratorClifford Wolf2019-07-252-3/+20
| |\ \ \ \ | | | | | | | | | | | | made ObjectIterator comply with Iterator Interface
| | * | | | replaced std::iterator with using statementsJakob Wenzel2019-07-251-6/+6
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| | * | | | made ObjectIterator extend std::iteratorJakob Wenzel2019-07-242-2/+19
| | |/ / / | | | | | | | | | | | | | | | this makes it possible to use std algorithms on them
| * | | | Merge pull request #1224 from YosysHQ/xilinx_fix_ffEddie Hung2019-07-251-2/+2
| |\ \ \ \ | | |_|_|/ | |/| | | xilinx: Fix missing cell name underscore in cells_map.v
| | * | | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | Merge pull request #1222 from koriakin/s6-exampleEddie Hung2019-07-245-0/+47
| |\ \ \ \ | | |_|/ / | |/| | | Add a simple example for Spartan 6
| | * | | Add a simple example for Spartan 6Marcin Kościelnicki2019-07-245-0/+47
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| * | | Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dspEddie Hung2019-07-233-9/+241
| |\ \ \ | | | | | | | | | | ice40: Fix SB_MAC16 sim model for signed modes
| | * | | ice40: Fix test_dsp_model.shDavid Shah2019-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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