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* | Rename "fine:" label to "map:" in "synth_ice40"Clifford Wolf2018-12-161-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #704 from webhat/feature/fix-awkClifford Wolf2018-12-161-2/+3
|\ \ | | | | | | Using awk rather than gawk
| * | Using awk rather than gawkDaniël W. Crompton2018-11-191-2/+3
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* | | Merge pull request #738 from smunaut/issue_737Clifford Wolf2018-12-161-19/+29
|\ \ \ | | | | | | | | verilog_parser: Properly handle recursion when processing attributes
| * | | verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
| | | | | | | | | | | | | | | | | | | | | | | | Fixes #737 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | | Merge pull request #735 from daveshah1/trifixesClifford Wolf2018-12-161-3/+4
|\ \ \ \ | | | | | | | | | | deminout fixes
| * | | | deminout: Consider $tribuf cellsDavid Shah2018-12-121-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | deminout: Don't demote constant-driven inouts to inputsDavid Shah2018-12-121-1/+2
| |/ / / | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #739 from whitequark/patch-1Clifford Wolf2018-12-161-0/+7
|\ \ \ \ | | | | | | | | | | Add .editorconfig file
| * | | | Add .editorconfig file.whitequark2018-12-161-0/+7
| | | | | | | | | | | | | | | See https://editorconfig.org/ for details.
* | | | | Fix equiv_opt indentingClifford Wolf2018-12-161-139/+129
|/ / / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-166-27/+173
|\ \ \ \ | | | | | | | | | | equiv_opt: new command, for verifying optimization passes
| * | | | equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-074-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models.
| * | | | equiv_opt: new command, for verifying optimization passes.whitequark2018-12-074-24/+169
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* | | | | Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdataClifford Wolf2018-12-161-0/+17
|\ \ \ \ \ | | | | | | | | | | | | memory_bram: Fix initdata bit order after shuffling
| * | | | | memory_bram: Fix initdata bit order after shufflingGraham Edgecombe2018-12-111-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases the memory_bram pass shuffles the order of the bits in a memory's RD_DATA port. Although the order of the bits in the WR_DATA and WR_EN ports is changed to match the RD_DATA port, the order of the bits in the initialization data is not. This causes reads of initialized memories to return invalid data (until the initialization data is overwritten). This commit fixes the bug by shuffling the initdata bits in exactly the same order as the RD_DATA/WR_DATA/WR_EN bits.
* | | | | | Merge pull request #730 from smunaut/ffssr_dont_touchClifford Wolf2018-12-161-0/+3
|\ \ \ \ \ \ | | | | | | | | | | | | | | ice40: Honor the "dont_touch" attribute in FFSSR pass
| * | | | | | ice40: Honor the "dont_touch" attribute in FFSSR passSylvain Munaut2018-12-081-0/+3
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is useful if you want to place FF manually ... can't merge SR in those because it might make the manual placement invalid Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | | | | Merge pull request #729 from whitequark/write_verilog_initialClifford Wolf2018-12-161-0/+2
|\ \ \ \ \ \ | | | | | | | | | | | | | | write_verilog: correctly map RTLIL `sync init`
| * | | | | | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
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* | | | | | Merge pull request #725 from olofk/ram4k-initClifford Wolf2018-12-161-0/+19
|\ \ \ \ \ \ | | | | | | | | | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosys
| * | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosysOlof Kindgren2018-12-061-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In an initial statement, blocking assignments are normally used and e.g. verilator throws a warning if non-blocking ones are used. Yosys cannot however properly resolve the interdependencies if blocking assignments are used in the initialization of SB_RAM_40_4K and thus this has been used. This patch will change to use non-blocking assignments only for yosys
* | | | | | | Merge pull request #714 from daveshah1/abc_preserve_namingClifford Wolf2018-12-161-29/+51
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Proof-of-concept: preserve naming through ABC using dress
| * | | | | | | abc: Preserve naming through ABC using 'dress' commandDavid Shah2018-12-061-29/+51
| |/ / / / / / | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | Merge pull request #723 from whitequark/synth_ice40_map_gatesClifford Wolf2018-12-161-0/+4
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | synth_ice40: split `map_gates` off `fine`
| * | | | | | | synth_ice40: split `map_gates` off `fine`.whitequark2018-12-061-0/+4
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* | | | | | | Merge pull request #722 from whitequark/rename_srcClifford Wolf2018-12-161-0/+50
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | rename: add -src, for inferring names from source locations
| * | | | | | | rename: add -src, for inferring names from source locations.whitequark2018-12-051-0/+50
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* | | | | | | Merge pull request #720 from whitequark/masterClifford Wolf2018-12-162-2/+2
|\ \ \ \ \ \ \ | |_|_|_|_|/ / |/| | | | | | lut2mux: handle 1-bit INIT constant in $lut cells
| * | | | | | lut2mux: handle 1-bit INIT constant in $lut cells.whitequark2018-12-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass already handles INIT constants shorter than 2^width, but that was not done for the recursion base case.
| * | | | | | opt_lut: simplify type conversion. NFC.whitequark2018-12-051-1/+1
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* | | | / / Add yosys-smtbmc support for btor witnessClifford Wolf2018-12-101-15/+100
| |_|_|/ / |/| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Add "yosys-smtbmc --btorwit" skeletonClifford Wolf2018-12-081-1/+19
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Fix btor init value handlingClifford Wolf2018-12-081-9/+13
| |_|/ / |/| | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #727 from whitequark/opt_lutDavid Shah2018-12-073-5/+50
|\ \ \ \ | |_|/ / |/| | | opt_lut: leave intact LUTs with cascade feeding module outputs
| * | | opt_lut: leave intact LUTs with cascade feeding module outputs.whitequark2018-12-073-0/+26
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| * | | opt_lut: show original truth table for both cells.whitequark2018-12-071-2/+3
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| * | | opt_lut: add -limit option, for debugging misoptimizations.whitequark2018-12-071-3/+21
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* | | Add missing .gitignoreClifford Wolf2018-12-061-0/+8
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Bugfix in opt_expr handling of a<0 and a>=0Clifford Wolf2018-12-061-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Verific updatesClifford Wolf2018-12-062-54/+1
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #709 from smunaut/issue_708Clifford Wolf2018-12-051-1/+1
|\ \ | | | | | | Make return value of $clog2 signed
| * | Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | Merge pull request #718 from whitequark/gate2lutClifford Wolf2018-12-0512-4/+151
|\ \ \ | | | | | | | | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs
| * | | synth_ice40: add -noabc option, to use built-in LUT techmapping.whitequark2018-12-051-2/+16
| | | | | | | | | | | | | | | | This should be combined with -relut to get sensible results.
| * | | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-0510-0/+133
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| * | | Fix typo.whitequark2018-12-051-2/+2
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* | | Merge pull request #713 from Diego-HR/masterClifford Wolf2018-12-055-12/+91
|\ \ \ | | | | | | | | Changes in GoWin synth commands and ALU primitive support
| * | | Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-035-12/+91
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* | | | Merge pull request #712 from mmicko/anlogic-supportClifford Wolf2018-12-057-0/+1278
|\ \ \ \ | | | | | | | | | | Initial support for Anlogic FPGA
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