| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | | * | | | memory_dff: Fix typo when checking init value | David Shah | 2018-12-18 | 1 | -1/+1 | |
| | |/ / / | ||||||
| | * | | | Fix segfault in AST simplify | Clifford Wolf | 2018-12-18 | 1 | -0/+5 | |
| | * | | | Improve src tagging (using names and attrs) of cells and wires in verific fro... | Clifford Wolf | 2018-12-18 | 2 | -99/+160 | |
| | |/ / | ||||||
| | * | | Merge pull request #746 from Icenowy/anlogic-dram | Clifford Wolf | 2018-12-17 | 5 | -1/+355 | |
| | |\ \ | | |/ | |/| | ||||||
| | | * | anlogic: add support for Eagle Distributed RAM | Icenowy Zheng | 2018-12-17 | 4 | -1/+43 | |
| | | * | Revert "Leave only real black box cells" | Icenowy Zheng | 2018-12-17 | 1 | -0/+312 | |
| | * | | Merge pull request #742 from whitequark/changelog | Clifford Wolf | 2018-12-17 | 1 | -0/+7 | |
| | |\ \ | ||||||
| | | * | | Update CHANGELOG. | whitequark | 2018-12-16 | 1 | -0/+7 | |
| | * | | | Merge pull request #741 from whitequark/ilang_slice_sigspec | Clifford Wolf | 2018-12-17 | 1 | -10/+6 | |
| | |\ \ \ | ||||||
| | | * | | | read_ilang: allow slicing sigspecs. | whitequark | 2018-12-16 | 1 | -10/+6 | |
| | | |/ / | ||||||
| | * | | | Merge pull request #744 from whitequark/write_verilog_$shift | Clifford Wolf | 2018-12-17 | 1 | -0/+29 | |
| | |\ \ \ | | |_|/ | |/| | | ||||||
| | | * | | write_verilog: handle the $shift cell. | whitequark | 2018-12-16 | 1 | -0/+29 | |
| | | |/ | ||||||
| | * | | Merge pull request #745 from YosysHQ/revert-714-abc_preserve_naming | Clifford Wolf | 2018-12-16 | 1 | -51/+29 | |
| | |\ \ | | |/ | |/| | ||||||
| | | * | Revert "Proof-of-concept: preserve naming through ABC using dress" | Clifford Wolf | 2018-12-16 | 1 | -51/+29 | |
| | |/ | ||||||
| | * | Merge pull request #736 from whitequark/select_assert_list | Clifford Wolf | 2018-12-16 | 2 | -9/+51 | |
| | |\ | ||||||
| | | * | select: print selection if a -assert-* flag causes an error. | whitequark | 2018-12-16 | 1 | -8/+50 | |
| | | * | write_verilog: add a missing newline. | whitequark | 2018-12-16 | 1 | -1/+1 | |
| | * | | Rename "fine:" label to "map:" in "synth_ice40" | Clifford Wolf | 2018-12-16 | 1 | -1/+1 | |
| | * | | Merge pull request #704 from webhat/feature/fix-awk | Clifford Wolf | 2018-12-16 | 1 | -2/+3 | |
| | |\ \ | ||||||
| | | * | | Using awk rather than gawk | Daniël W. Crompton | 2018-11-19 | 1 | -2/+3 | |
| | * | | | Merge pull request #738 from smunaut/issue_737 | Clifford Wolf | 2018-12-16 | 1 | -19/+29 | |
| | |\ \ \ | ||||||
| | | * | | | verilog_parser: Properly handle recursion when processing attributes | Sylvain Munaut | 2018-12-14 | 1 | -19/+29 | |
| | * | | | | Merge pull request #735 from daveshah1/trifixes | Clifford Wolf | 2018-12-16 | 1 | -3/+4 | |
| | |\ \ \ \ | ||||||
| | | * | | | | deminout: Consider $tribuf cells | David Shah | 2018-12-12 | 1 | -2/+2 | |
| | | * | | | | deminout: Don't demote constant-driven inouts to inputs | David Shah | 2018-12-12 | 1 | -1/+2 | |
| | | |/ / / | ||||||
| | * | | | | Merge pull request #739 from whitequark/patch-1 | Clifford Wolf | 2018-12-16 | 1 | -0/+7 | |
| | |\ \ \ \ | ||||||
| | | * | | | | Add .editorconfig file. | whitequark | 2018-12-16 | 1 | -0/+7 | |
| | * | | | | | Fix equiv_opt indenting | Clifford Wolf | 2018-12-16 | 1 | -139/+129 | |
| | |/ / / / | ||||||
| | * | | | | Merge pull request #724 from whitequark/equiv_opt | Clifford Wolf | 2018-12-16 | 6 | -27/+173 | |
| | |\ \ \ \ | ||||||
| | | * | | | | equiv_opt: pass -D EQUIV when techmapping. | whitequark | 2018-12-07 | 4 | -6/+7 | |
| | | * | | | | equiv_opt: new command, for verifying optimization passes. | whitequark | 2018-12-07 | 4 | -24/+169 | |
| | * | | | | | Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata | Clifford Wolf | 2018-12-16 | 1 | -0/+17 | |
| | |\ \ \ \ \ | ||||||
| | | * | | | | | memory_bram: Fix initdata bit order after shuffling | Graham Edgecombe | 2018-12-11 | 1 | -0/+17 | |
| | * | | | | | | Merge pull request #730 from smunaut/ffssr_dont_touch | Clifford Wolf | 2018-12-16 | 1 | -0/+3 | |
| | |\ \ \ \ \ \ | ||||||
| | | * | | | | | | ice40: Honor the "dont_touch" attribute in FFSSR pass | Sylvain Munaut | 2018-12-08 | 1 | -0/+3 | |
| | | |/ / / / / | ||||||
| | * | | | | | | Merge pull request #729 from whitequark/write_verilog_initial | Clifford Wolf | 2018-12-16 | 1 | -0/+2 | |
| | |\ \ \ \ \ \ | ||||||
| | | * | | | | | | write_verilog: correctly map RTLIL `sync init`. | whitequark | 2018-12-07 | 1 | -0/+2 | |
| | | | |_|_|_|/ | | |/| | | | | ||||||
| | * | | | | | | Merge pull request #725 from olofk/ram4k-init | Clifford Wolf | 2018-12-16 | 1 | -0/+19 | |
| | |\ \ \ \ \ \ | ||||||
| | | * | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosys | Olof Kindgren | 2018-12-06 | 1 | -0/+19 | |
| | * | | | | | | | Merge pull request #714 from daveshah1/abc_preserve_naming | Clifford Wolf | 2018-12-16 | 1 | -29/+51 | |
| | |\ \ \ \ \ \ \ | ||||||
| | | * | | | | | | | abc: Preserve naming through ABC using 'dress' command | David Shah | 2018-12-06 | 1 | -29/+51 | |
| | | |/ / / / / / | ||||||
| | * | | | | | | | Merge pull request #723 from whitequark/synth_ice40_map_gates | Clifford Wolf | 2018-12-16 | 1 | -0/+4 | |
| | |\ \ \ \ \ \ \ | ||||||
| | | * | | | | | | | synth_ice40: split `map_gates` off `fine`. | whitequark | 2018-12-06 | 1 | -0/+4 | |
| | | | |_|_|/ / / | | |/| | | | | | ||||||
| | * | | | | | | | Merge pull request #722 from whitequark/rename_src | Clifford Wolf | 2018-12-16 | 1 | -0/+50 | |
| | |\ \ \ \ \ \ \ | ||||||
| | | * | | | | | | | rename: add -src, for inferring names from source locations. | whitequark | 2018-12-05 | 1 | -0/+50 | |
| | | |/ / / / / / | ||||||
| | * | | | | | | | Merge pull request #720 from whitequark/master | Clifford Wolf | 2018-12-16 | 2 | -2/+2 | |
| | |\ \ \ \ \ \ \ | | |_|_|_|_|/ / | |/| | | | | | | ||||||
| | | * | | | | | | lut2mux: handle 1-bit INIT constant in $lut cells. | whitequark | 2018-12-05 | 1 | -1/+1 | |
| | | * | | | | | | opt_lut: simplify type conversion. NFC. | whitequark | 2018-12-05 | 1 | -1/+1 | |
| | | |/ / / / / | ||||||
| | * | | | / / | Add yosys-smtbmc support for btor witness | Clifford Wolf | 2018-12-10 | 1 | -15/+100 | |
| | | |_|_|/ / | |/| | | | | ||||||
| | * | | | | | Add "yosys-smtbmc --btorwit" skeleton | Clifford Wolf | 2018-12-08 | 1 | -1/+19 | |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |