| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add bwmuxmap pass | Jannis Harder | 2022-11-30 | 7 | -0/+76 |
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| * | Add bitwise `$bweqx` and `$bwmux` cells | Jannis Harder | 2022-11-30 | 9 | -11/+179 |
| | | | | | | | The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals. | ||||
| * | verilog_backend: Do not run bmuxmap or demuxmap in -noexpr mode. | Jannis Harder | 2022-11-30 | 1 | -2/+4 |
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| * | verilog_backend: Correctly sign extend output of signed `$modfloor` | Jannis Harder | 2022-11-30 | 1 | -2/+2 |
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| * | verilog_backend: Add -noparallelcase option | Jannis Harder | 2022-11-30 | 1 | -7/+31 |
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| * | simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal | Jannis Harder | 2022-11-30 | 1 | -2/+8 |
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| * | simlib: Silence iverilog warning for `$lut` | Jannis Harder | 2022-11-30 | 1 | -1/+1 |
| | | | | | | | iverilog complains about implicitly truncating LUT when connecting it to the `$bmux` A input. This explicitly truncates it to avoid that warning without changing the behaviour otherwise. | ||||
| * | simlib: Fix wide $bmux and avoid iverilog warnings | Jannis Harder | 2022-11-30 | 1 | -2/+2 |
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| * | satgen, simlib: Consistent x-propagation for `$pmux` cells | Jannis Harder | 2022-11-30 | 2 | -18/+20 |
| | | | | | | This updates satgen and simlib to use a `$pmux` model where the output is fully X when the S input is not all zero or one-hot with no x bits. | ||||
| * | opt_expr: Fix shift/shiftx optimizations | Jannis Harder | 2022-11-30 | 1 | -3/+3 |
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| * | opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cells | Jannis Harder | 2022-11-29 | 1 | -0/+33 |
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| * | opt_expr: Optimize bitwise logic ops with one fully const input | Jannis Harder | 2022-11-29 | 1 | -0/+81 |
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| * | simplemap: Map `$xnor` to `$_XNOR_` cells | Jannis Harder | 2022-11-29 | 3 | -20/+5 |
| | | | | | | The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of the `$_XNOR_` cell. | ||||
| * | Bump version | github-actions[bot] | 2022-11-29 | 1 | -1/+1 |
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| * | Merge pull request #3565 from jix/sat-def-formal | Jannis Harder | 2022-11-28 | 3 | -10/+46 |
| |\ | | | | | sat: Add -set-def-formal option to force defined $any* outputs | ||||
| | * | sat: Add -set-def-formal option to force defined $any* outputs | Jannis Harder | 2022-11-28 | 3 | -10/+46 |
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| * | Bump version | github-actions[bot] | 2022-11-26 | 1 | -1/+1 |
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| * | Merge pull request #3561 from YosysHQ/tcl_shell | Miodrag Milanović | 2022-11-25 | 2 | -8/+34 |
| |\ | | | | | Add TCL interactive shell mode | ||||
| | * | Add TCL interactive shell mode | Miodrag Milanovic | 2022-11-25 | 2 | -8/+34 |
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| * | | Merge pull request #3560 from YosysHQ/verific_conf | Miodrag Milanović | 2022-11-25 | 3 | -8/+43 |
| |\ \ | |/ |/| | Support importing verilog configurations using Verific | ||||
| | * | update documentation | Miodrag Milanovic | 2022-11-25 | 1 | -3/+3 |
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| | * | Support importing verilog configurations using Verific | Miodrag Milanovic | 2022-11-25 | 3 | -5/+40 |
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| * | | Bump version | github-actions[bot] | 2022-11-25 | 1 | -1/+1 |
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| * | | Remove docs dependency on yosys repo (#3558) | KrystalDelusion | 2022-11-24 | 39 | -18/+905 |
| |/ | | | | | | | | | | | * Copies guidelines files into docs/ for website * Copying manual/CHAPTER_Prog for new docs * Copying manual/APPNOTE_011... for new docs Also adding faketime to list of packages for website build. Co-authored-by: KrystalDelusion <krystinedawn@yosyshq.com> | ||||
| * | Merge pull request #3552 from daglem/fix-sv-c-array-dimensions | Jannis Harder | 2022-11-23 | 1 | -3/+3 |
| |\ | | | | | Correct interpretation of SystemVerilog C-style array dimensions | ||||
| | * | Correct interpretation of SystemVerilog C-style array dimensions | Dag Lem | 2022-11-13 | 1 | -3/+3 |
| | | | | | | | | | IEEE Std 1800™-2017 7.4.2 specifies that [size] is the same as [0:size-1]. | ||||
| * | | Bump version | github-actions[bot] | 2022-11-22 | 1 | -1/+1 |
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| * | | Merge branch 'zachjs-master' | Jannis Harder | 2022-11-21 | 3 | -0/+52 |
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| | * | | verilog: Support module-scoped task/function calls | Zachary Snow | 2022-10-29 | 3 | -0/+52 |
| | | | | | | | | | | | | | | | | | | | | | | | | | This is primarily intended to enable the standard-permitted use of module-scoped identifiers to refer to tasks and non-constant functions. As a side-effect, this also adds support for the non-standard use of module-scoped identifiers referring to constant functions, a feature that is supported in some other tools, including Iverilog. | ||||
| * | | | mention prerequisites in fsm_detect and fsm help | N. Engelhardt | 2022-11-21 | 2 | -0/+18 |
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| * | | | Bump version | github-actions[bot] | 2022-11-18 | 1 | -1/+1 |
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| * | | | fabulous: Allow adding extra custom prims and map rules | gatecat | 2022-11-17 | 4 | -0/+53 |
| | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | | fabulous: improvements to the pass | gatecat | 2022-11-17 | 13 | -139/+340 |
| | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | | fabulous: Unify and update primitives | gatecat | 2022-11-17 | 3 | -852/+356 |
| | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | | Introduce RegFile mappings | TaoBi22 | 2022-11-17 | 4 | -2/+95 |
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| * | | | Replace synth call with components, reintroduce flags and correct vpr flag ↵ | TaoBi22 | 2022-11-17 | 1 | -4/+76 |
| | | | | | | | | | | | | | implementation | ||||
| * | | | Reorder operations to load in primitive library before hierarchy pass | TaoBi22 | 2022-11-17 | 1 | -5/+6 |
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| * | | | Add plib flag to specify custom primitive library path | TaoBi22 | 2022-11-17 | 1 | -2/+14 |
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| * | | | Remove flattening from FABulous pass | TaoBi22 | 2022-11-17 | 1 | -11/+2 |
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| * | | | Remove ALL currently unused flags (some to be reintroduced later and passed ↵ | TaoBi22 | 2022-11-17 | 1 | -82/+3 |
| | | | | | | | | | | | | | through to synth) | ||||
| * | | | Add synth_fabulous ScriptPass | TaoBi22 | 2022-11-17 | 8 | -0/+1282 |
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| * | | | Bump version | github-actions[bot] | 2022-11-17 | 1 | -1/+1 |
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| * | | | Slowing down clock to have same metadata | Miodrag Milanovic | 2022-11-16 | 1 | -2/+2 |
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| * | | | Bump version | github-actions[bot] | 2022-11-16 | 1 | -1/+1 |
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| * | | | faketime to make PDFs unique | Miodrag Milanovic | 2022-11-15 | 1 | -2/+2 |
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| * | | | Rst docs conversion (#3496) | KrystalDelusion | 2022-11-15 | 57 | -2/+7792 |
| | | | | | | | | | | Rst docs conversion | ||||
| * | | | Merge pull request #3547 from YosysHQ/update_abc | Miodrag Milanović | 2022-11-14 | 1 | -1/+1 |
| |\ \ \ | |_|/ |/| | | Update ABC | ||||
| | * | | Update ABC | Miodrag Milanovic | 2022-11-09 | 1 | -1/+1 |
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| * | | | Bump version | github-actions[bot] | 2022-11-10 | 1 | -1/+1 |
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| * | | | Add missing memory width assert preventing division by zero (#3546) | Emil J | 2022-11-09 | 1 | -0/+1 |
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