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* Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-2215-23/+591
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| * Add to CHANGELOGEddie Hung2019-11-221-0/+1
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| * New 'clkpart' to {,un}partition design according to clock/enableEddie Hung2019-11-221-0/+268
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| * Merge pull request #1517 from YosysHQ/clifford/optmemClifford Wolf2019-11-223-0/+146
| |\ | | | | | | Add "opt_mem" pass
| | * Add "opt_mem" passClifford Wolf2019-11-223-0/+146
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1515 from YosysHQ/clifford/svastuffClifford Wolf2019-11-222-7/+39
| |\ \ | | |/ | |/| Add Verific/SVA support for "always" and "nexttime" properties
| | * Add Verific support for SVA nexttime propertiesClifford Wolf2019-11-221-0/+22
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Improve handling of verific primitives in "verific -import -V" modeClifford Wolf2019-11-221-2/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add Verific SVA support for "always" propertiesClifford Wolf2019-11-221-5/+15
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #1511 from YosysHQ/dave/alwaysClifford Wolf2019-11-226-9/+126
| |\ | | | | | | sv: Error checking for always_comb, always_latch and always_ff
| | * Update CHANGELOG and READMEDavid Shah2019-11-222-0/+7
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Add tests for SV always typesDavid Shah2019-11-211-0/+63
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usageDavid Shah2019-11-211-4/+16
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-212-5/+40
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | gowin: Remove show command from tests.Marcin Kościelnicki2019-11-221-1/+0
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| * | gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
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| * Merge pull request #1507 from YosysHQ/clifford/verificfixesClifford Wolf2019-11-202-6/+9
| |\ | | | | | | Some fixes in our Verific integration
| | * Correctly treat empty modules as blackboxes in VerificClifford Wolf2019-11-201-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Do not rename VHDL entities to "entity(impl)" when they are top modulesClifford Wolf2019-11-202-5/+8
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Revert "write_xaiger to not use module POs but only write outputs if driven"Eddie Hung2019-11-221-23/+11
| | | | | | | | This reverts commit 0ab1e496dc601f8e9d5efbcc5b2be7cf6b2d9673.
* | Missing endmoduleEddie Hung2019-11-221-0/+1
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* | write_xaiger to not use module POs but only write outputs if drivenEddie Hung2019-11-211-11/+23
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* | When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_Eddie Hung2019-11-211-1/+1
| | | | | | | | Since they should be captured downwards from the owning flop
* | Merge branch 'eddie/xaig_dff_adff' into xaig_dffEddie Hung2019-11-215-16/+55
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| * | Add a equiv test tooEddie Hung2019-11-192-0/+23
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| * | Add two testsEddie Hung2019-11-191-0/+12
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| * | abc9 to support async flops $_DFF_[NP][NP][01]_Eddie Hung2019-11-191-1/+2
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| * | Do not drop async control signals in abc_map.vEddie Hung2019-11-191-12/+16
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* | | Add testEddie Hung2019-11-211-1/+6
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* | | Consistent log message, ignore 's' extensionEddie Hung2019-11-201-2/+3
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* | | endomain -> ctrldomainEddie Hung2019-11-201-3/+3
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* | | Add blackbox model for $__ABC9_FF_ so that clock partitioning worksEddie Hung2019-11-201-0/+3
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* | | Add multi clock testEddie Hung2019-11-201-0/+5
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* | | Fix INIT valuesEddie Hung2019-11-201-4/+4
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-19228-24028/+35109
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| * Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-1927-89/+841
| |\ | | | | | | Improvements for gowin support
| | * Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| | | | | | | | | | | | | | | The hardware does not actually support it. In reality it is always initialised to its reset value.
| | * add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
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| | * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1615-47/+913
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| | * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-112-4/+15
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| | * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1129-23010/+30701
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| | * | | fix wide lutsPepijn de Vos2019-11-062-19/+22
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| | * | | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
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| | * | | add IOBUFPepijn de Vos2019-10-282-1/+10
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| | * | | add tristate buffer and testPepijn de Vos2019-10-283-2/+21
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| | * | | do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
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| | * | | actually run the gowin testsPepijn de Vos2019-10-281-0/+1
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| | * | | More formattingPepijn de Vos2019-10-281-55/+49
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| | * | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
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| | * | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
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