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* | Added support for dlatchsr cellsClifford Wolf2014-03-315-1/+207
* | Fixed mapping of Verific WIDE_DFFRS operatorClifford Wolf2014-03-201-2/+2
* | Fixed mapping of Verific FADD primitive with unconnected outputsClifford Wolf2014-03-201-4/+5
* | Fixed performance problem in opt_mux with nets driven by many conflicting dri...Clifford Wolf2014-03-191-1/+6
* | Progress in Verific bindingsClifford Wolf2014-03-171-8/+51
* | Fixed typo in RTLIL::Module::addAdff()Clifford Wolf2014-03-171-1/+1
* | Progress in Verific bindingsClifford Wolf2014-03-171-5/+50
* | Progress in Verific bindingsClifford Wolf2014-03-174-2/+15
* | Added support for memories to verific bindingsClifford Wolf2014-03-162-1/+86
* | Use Verific Net::{IsGnd,IsPwr} API in Verific bindingsClifford Wolf2014-03-161-27/+11
* | Fixed typo in RTLIL::Module::{addSshl,addSshr}Clifford Wolf2014-03-151-2/+2
* | Progress in Verific bindingsClifford Wolf2014-03-151-39/+16
* | Progress in Verific bindingsClifford Wolf2014-03-151-7/+15
* | Progress in Verific bindingsClifford Wolf2014-03-151-31/+31
* | Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() APIClifford Wolf2014-03-152-1/+61
* | Progress in Verific bindingsClifford Wolf2014-03-141-13/+38
* | Added log_dump() support for generic pointersClifford Wolf2014-03-141-0/+3
* | Progress in Verific bindingsClifford Wolf2014-03-143-228/+348
* | Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate APIClifford Wolf2014-03-142-0/+48
* | Progress in Verific bindingsClifford Wolf2014-03-131-10/+65
* | Copy Verific vdbs files to Yosys "share" data directoryClifford Wolf2014-03-133-9/+24
* | Small improvement in SAT log messagesClifford Wolf2014-03-131-3/+3
* | Added test_navre.ys for verific frontendClifford Wolf2014-03-131-0/+17
* | Hotfix for kernel/compatibility.hClifford Wolf2014-03-131-1/+2
* | Merge branch 'master' of https://github.com/Siesh1oo/yosysClifford Wolf2014-03-130-0/+0
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| * | - Makefile, kernel/posix_compatibility.h/.cc: replay isolated OSX/POSIX.2008...Siesh1oo2014-03-133-9/+194
| * | Merge branch 'master' of https://github.com/Siesh1oo/yosysSiesh1oo2014-03-132-24/+7
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| | * | - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...Siesh1oo2014-03-126-39/+44
| | * | - Makefile: don't export DYLD_LIBRARY_PATH/LD_LIBRARY_PATH: not needed if we...Siesh1oo2014-03-121-2/+0
| | * | - .gitignore: ignore qmake/OSX package libs/svgviewer/svgviewer.appSiesh1oo2014-03-121-0/+1
| | * | - Makefile: follow changes in https://github.com/cliffordwolf/yosysSiesh1oo2014-03-121-16/+3
| | * | - libs/minisat/Solver.cc: insert spaces between string and PRIu64 literal, o...Siesh1oo2014-03-121-5/+5
| | * | - libs/minisat/System.cc: fix definition/declaration mismatch for Minisat::m...Siesh1oo2014-03-121-3/+3
| | * | Merge branch 'master' of https://github.com/Siesh1oo/yosysSiesh1oo2014-03-124-6/+190
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| | | * | - Makefile: don't add '-g' after '-ggdb' to CXXFLAGSSiesh1oo2014-03-111-2/+2
| | | * | Rebase to cliffordwolf repo HEAD finished.Siesh1oo2014-03-114-6/+190
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| | | | * | - passes/techmap/Makefile.inc: POSIX 'od' has no '-w' option. Use '-An' inst...Siesh1oo2014-03-111-4/+6
| | | | * | - Makefile: include $(PWD) in PATH, since 'make test' can happen before 'mak...Siesh1oo2014-03-101-1/+1
| | | | * | - libs/ezsat/ezminisat.cc: use sigemptyset() to clear sig_action.sa_mask; us...Siesh1oo2014-03-101-2/+2
| | | | * | - Makefile: fix typo in LDFLAGS: obviously -L, not -I is required hereSiesh1oo2014-03-101-1/+1
| | | | * | - Makefile: export PATH=${DESTDIR}/bin:$(PATH) and (DY)LD_LIBRARY_PATH, to m...Siesh1oo2014-03-101-2/+6
| | | | * | - frontends/vhdl2verilog/vhdl2verilog.cc, passes/abc/abc.cc: #include <climi...Siesh1oo2014-03-102-0/+2
| | | | * | - Makefile, techlibs/common/Makefile.inc: call GNU sed instead of BSD sed on...Siesh1oo2014-03-102-3/+5
| | | | * | - libs/ezsat/ezminisat.cc: use POSIX.2001 sigaction() instead on non-portabl...Siesh1oo2014-03-101-4/+8
| | | | * | - Makefile, kernel/posix_compatibility.h/.cc: provide POSIX.2008 fake implem...Siesh1oo2014-03-104-10/+211
| | | | * | - README: fix typo in sed-command for minisat-include fix.Siesh1oo2014-03-101-1/+1
| | | | * | - frontends/vhdl2verilog/vhdl2verilog.cc: #include <cerrno> for errno; use P...Siesh1oo2014-03-101-4/+11
| | | | * | - kernel/register.cc: need to #include <cerrno> or errno.h for errno.Siesh1oo2014-03-101-0/+1
| | | | * | - kernel/driver.cc: need to #include <cerrno> or errno.h for errno.Siesh1oo2014-03-101-0/+1
| | | | * | - kernel/log.h: add rusage()-based fallback for systems without clock_gettim...Siesh1oo2014-03-101-0/+16