aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Also look for yosys-abc in parent dir on win32Clifford Wolf2014-10-181-0/+5
|
* Various improvements to version reporting on win32Clifford Wolf2014-10-183-11/+23
|
* Disabled READLINE in MXE cross buildClifford Wolf2014-10-181-0/+1
|
* Fixed typo in test_cellClifford Wolf2014-10-181-1/+1
|
* Fixed shell prompt and proc_self_dirname() for win32Clifford Wolf2014-10-181-6/+24
|
* Fixed various VS warningsClifford Wolf2014-10-188-14/+14
|
* Create vcxsrc in mxe build "make dist"Clifford Wolf2014-10-184-33/+78
|
* Moved yosys-config.in to misc/Clifford Wolf2014-10-182-2/+2
|
* Added notes regarding building in VSClifford Wolf2014-10-172-3/+38
|
* Added vcxproj_files.txt to MXE "make dist"Clifford Wolf2014-10-171-5/+7
|
* More win32 (mxe and vs) build fixesClifford Wolf2014-10-175-25/+86
|
* Various win32 / vs build fixesClifford Wolf2014-10-178-23/+28
|
* Added genfiles.zip to MXE "make dist"Clifford Wolf2014-10-172-2/+4
|
* Various MXE build fixesClifford Wolf2014-10-174-13/+28
|
* Header changes so it will compile on VSWilliam Speirs2014-10-1710-17/+79
|
* Wrapped math in int constructorWilliam Speirs2014-10-171-1/+1
|
* Fixed a few VS warningsClifford Wolf2014-10-173-3/+3
|
* Don't be too smart with $dff cells with "init" attribute on out signalClifford Wolf2014-10-161-1/+1
|
* Some cleanups in opt_cleanClifford Wolf2014-10-161-16/+9
|
* Print "SystemVerilog" in "read_verilog -sv" log messagesClifford Wolf2014-10-161-1/+1
|
* Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selectsClifford Wolf2014-10-161-1/+8
|
* Fixed handling of invalid array access in mem2reg codeClifford Wolf2014-10-162-3/+15
|
* Replaced log_assert() do { ... } while (0) hack with a static inline functionClifford Wolf2014-10-151-1/+5
|
* Fixed gcc warningClifford Wolf2014-10-151-1/+2
|
* Fixed MXE buildClifford Wolf2014-10-152-3/+3
|
* Merge branch 'win32'Clifford Wolf2014-10-1518-71/+105
|\
| * Check for _YOSYS_ in yosys.hClifford Wolf2014-10-151-0/+6
| |
| * Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-152-8/+8
| |
| * Replaced readsome() with read() and gcount()Clifford Wolf2014-10-154-23/+11
| |
| * A few indent fixesClifford Wolf2014-10-153-4/+4
| |
| * Changed from "and" to "&&"William Speirs2014-10-151-1/+1
| |
| * Changed to explicit heap allocated memoryWilliam Speirs2014-10-151-1/+4
| |
| * Wrapped init in std::set constructorWilliam Speirs2014-10-151-2/+2
| |
| * Made iterators extend std::iterator and added == operatorWilliam Speirs2014-10-151-2/+4
| |
| * Define empty __attribute__ macro for non-gcc, non-clang compilersClifford Wolf2014-10-152-13/+9
| |
| * Fixed log so it will compile under Visual StudioWilliam Speirs2014-10-152-8/+39
| | | | | | | | - Included an implementation of gettimeofday
| * Updated lexers & parsers to include prefixesWilliam Speirs2014-10-156-27/+35
|/
* Updated ABC, enabled ABC in mxe buildsClifford Wolf2014-10-151-3/+2
|
* Removed CHECK() macro from libparse.cc (was using non-std c features)Clifford Wolf2014-10-131-22/+15
|
* Fixed ABC ARCHFLAGS for win32 cross buildClifford Wolf2014-10-121-1/+1
|
* More win32/abc fixesClifford Wolf2014-10-123-45/+46
|
* Various Makefile changes for cross-compiling ABC for Win32Clifford Wolf2014-10-122-8/+12
|
* Various small fixes for non-win32 buildsClifford Wolf2014-10-122-4/+11
|
* Added make_temp_{file,dir}() and remove_directory() APIsClifford Wolf2014-10-124-49/+116
|
* Using stringf() instead of asprintf() in "abc" passClifford Wolf2014-10-121-29/+24
|
* Added run_command() api to replace system() and popen()Clifford Wolf2014-10-126-92/+104
|
* Renamed "log.cc" to "logcmd.cc" so there aren't two "log.cc" in the source treeClifford Wolf2014-10-112-1/+1
|
* Shrinked the copyright banner by 1 characterClifford Wolf2014-10-111-19/+19
|
* Added "make dist" for mxe buildsClifford Wolf2014-10-111-0/+10
|
* Fixed Makefile PRETTY=1 for MXE (win32) and EMCC (js) buildsClifford Wolf2014-10-111-2/+2
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 06:02:21 +0000