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* synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
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* Merge pull request #1183 from whitequark/ice40-always-relutClifford Wolf2019-07-121-11/+5
|\ | | | | synth_ice40: switch -relut to be always on
| * synth_ice40: switch -relut to be always on.whitequark2019-07-111-10/+4
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| * synth_ice40: fix help text typo. NFC.whitequark2019-07-111-1/+1
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* | Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
|\ \ | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support.
| * | synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
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* | Merge pull request #1185 from koriakin/xc-ff-init-valsEddie Hung2019-07-112-6/+6
|\ \ | | | | | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
| * | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵Marcin Kościelnicki2019-07-112-6/+6
| |/ | | | | | | ISE/Vivado.
* / Enable &mfs for abc9, even if it only currently works for ice40Eddie Hung2019-07-111-1/+1
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* Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
|\ | | | | write_verilog: write RTLIL::Sa aka - as Verilog ?
| * write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
| | | | | | | | | | | | | | Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog.
* | Merge pull request #1179 from whitequark/attrmap-procClifford Wolf2019-07-111-0/+19
|\ \ | | | | | | attrmap: also consider process, switch and case attributes
| * | attrmap: also consider process, switch and case attributes.whitequark2019-07-101-0/+19
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* | | Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-103-6/+15
|\ \ \ | | | | | | | | Error out if -abc9 and -retime specified
| * | | Error out if -abc9 and -retime specifiedEddie Hung2019-07-103-6/+15
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* | | Merge pull request #1148 from YosysHQ/xc7muxEddie Hung2019-07-107-49/+415
|\ \ \ | | | | | | | | synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
| * | | Add some spacingEddie Hung2019-07-101-9/+9
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| * | | Add some ASCII art explaining mux decompositionEddie Hung2019-07-101-0/+21
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| * | | Call muxpack and pmux2shiftx before cmp2lutEddie Hung2019-07-091-9/+12
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| * | | Restore opt_clean back to original placeEddie Hung2019-07-091-2/+1
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| * | | Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6Eddie Hung2019-07-091-0/+2
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| * | | Extend using A[1] to preserve don't careEddie Hung2019-07-091-1/+9
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| * | | Merge remote-tracking branch 'origin/eddie/fix1173' into xc7muxEddie Hung2019-07-092-4/+9
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| * | | | Extend during mux decomposition with 1'bxEddie Hung2019-07-091-24/+3
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| * | | | Fix typo and commentsEddie Hung2019-07-091-4/+4
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| * | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-0916-79/+348
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| * | | | synth_xilinx to call commands of synth -coarse directlyEddie Hung2019-07-091-3/+20
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| * | | | Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""Eddie Hung2019-07-091-2/+2
| | | | | | | | | | | | | | | | | | | | This reverts commit 7f964859ec99500e471853f5914b6e5b7c35a031.
| * | | | Fix spacingEddie Hung2019-07-091-1/+1
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| * | | | Fix spacingEddie Hung2019-07-091-1/+1
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| * | | | Decompose mux inputs in delay-orientated (rather than area) fashionEddie Hung2019-07-081-18/+30
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| * | | | Do not call opt -mux_undef (part of -full) before muxcoverEddie Hung2019-07-081-1/+5
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| * | | | Add one more commentEddie Hung2019-07-081-0/+3
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| * | | | Less thinkingEddie Hung2019-07-081-3/+3
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| * | | | RewordEddie Hung2019-07-081-2/+2
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| * | | | synth_xilinx to call "synth -run coarse" with "-keepdc"Eddie Hung2019-07-081-2/+2
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| * | | | Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7muxEddie Hung2019-07-084-8/+25
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| * | | | | Map $__XILINX_SHIFTX in a more balanced mannerEddie Hung2019-07-081-36/+49
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| * | | | | CapitalisationEddie Hung2019-07-081-1/+1
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| * | | | | Add synth_xilinx -widemux recommended valueEddie Hung2019-07-081-1/+1
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| * | | | | Fixes for 2:1 muxesEddie Hung2019-07-082-5/+30
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| * | | | | synth_xilinx -widemux=2 is minimum nowEddie Hung2019-07-081-4/+7
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| * | | | | Parametric muxcover costs as per @daveshah1Eddie Hung2019-07-081-16/+14
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| * | | | | Merge remote-tracking branch 'origin/eddie/muxcover_mux2' into xc7muxEddie Hung2019-07-081-5/+11
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| * | | | | | atoi -> stoi as per @daveshah1Eddie Hung2019-07-081-1/+1
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| * | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-088-90/+60
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| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-024-3/+27
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| * \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/script_from_wire' into xc7muxEddie Hung2019-07-023-10/+13
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| * | | | | | | | | Fix $__XILINX_MUXF78 box timingEddie Hung2019-07-011-1/+1
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| * | | | | | | | | Revert "Fix broken MUXFx box, use MUXF7x2 box instead"Eddie Hung2019-07-013-37/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit a9a140aa6c84e71edc1a244cfe363400c7e09d90.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 20:56:23 +0000